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lxt386 quad t1/e1/j1 transceiver datasheet the lxt386 is a quad short haul pulse code modulation (pcm) transceiver for use in both 1.544 mbps (t1) and 2.048 mbps (e1) applications. it incorporates four independent receivers and four independent transmitters in a single pbga-160 or lqfp-100 package. the transmit drivers provide low impedance independent of the transmit pattern and supply voltage variations.the lxt386 transmits shaped waveforms meeting g.703 and t1.102 specifications. the lxt386 exceeds the latest transmit return loss specifications, such as etsi ets-300166. the lxt386?s differential receiver architecture provides high noise interference margin and is able to work with up to 12 db of cable attenuation. the digital clock recovery pll and jitter attenuator are referenced to a low frequency 1.544 mhz or 2.048 mhz clock. the lxt386 incorporates an advanced crystal-less jitter attenuator switchable between the receive and transmit path. the jitter attenuation performance meets the latest international specifications such as ctr12/13. the jitter attenuation performance was optimized for synchronous optical network/synchronous digital hierarchy (sonet/sdh) applications. the lxt386 can be configured as a 3 channel transceiver with g.772 compliant non intrusive protected monitoring points. it uses a single 3.3v supply for low power consumption. the constant delay characteristic of the lxt386 ja as well as a power down mode of all transmitters allows the implementation of hitless protection switching (hps) applications without the use of relays. applications sonet/sdh tributary interfaces digital cross connects public/private switching trunk line interfaces microwave transmission systems m13, e1-e3 mux order number: 249253-002 . november 2005
datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the lxt386 may contain design defects or errors known as errata which may cause the product to deviate from published specifica tions. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2005 *third-party brands and names are the property of their respective owners.
datasheet 3 quad t1/e1/j1 transceiver ? lxt386 contents 1.0 features .........................................................................................................................7 2.0 pin assignments and signal description ........................................................9 3.0 functional description ...........................................................................................22 3.1 initialization..........................................................................................................22 3.1.1 reset operation .....................................................................................23 3.2 receiver ..............................................................................................................24 3.2.1 loss of signal detector .......................................................................... 25 3.2.1.1 e1 mode ....................................................................................25 3.2.1.2 t1 mode ....................................................................................25 3.2.1.3 data recovery mode.................................................................25 3.2.2 alarm indication signal (ais) detection .................................................26 3.2.2.1 e1 mode ....................................................................................26 3.2.2.2 t1 mode ....................................................................................26 3.2.3 in service code violation monitoring ..................................................... 26 3.3 transmitter ..........................................................................................................27 3.3.1 transmit pulse shaping .........................................................................28 3.3.1.1 hardware mode .........................................................................28 3.3.1.2 host mode .................................................................................28 3.3.2 transmit pulse shaping .........................................................................29 3.3.2.1 output driver power supply ...................................................... 29 3.3.2.2 power sequencing .................................................................... 29 3.4 driver failure monitor..........................................................................................30 3.5 line protection ....................................................................................................30 3.6 jitter attenuation .................................................................................................32 3.7 loopbacks ........................................................................................................... 34 3.7.1 analog loopback.................................................................................... 34 3.7.2 digital loopback .....................................................................................34 3.7.3 remote loopback .................................................................................. 35 3.7.4 transmit all ones (taos)......................................................................36 3.8 g.772 performance monitoring ........................................................................... 37 3.9 hitless protection switching (hps) .....................................................................37 3.10 operation mode summary ..................................................................................38 3.11 interfacing with 5v logic ......................................................................................38 3.12 parallel host interface .........................................................................................39 3.12.1 motorola interface ..................................................................................40 3.12.2 intel interface..........................................................................................40 3.13 interrupt handling................................................................................................ 41 3.13.1 interrupt enable......................................................................................41 3.13.2 interrupt clear ........................................................................................41 3.14 serial host mode.................................................................................................42 4.0 register descriptions .............................................................................................43 5.0 jtag boundary scan .............................................................................................50 5.1 overview .............................................................................................................50 5.2 architecture .........................................................................................................50
lxt386 ? quad t1/e1/j1 transceiver 4 datasheet 5.3 tap controller.....................................................................................................51 5.4 jtag register description..................................................................................53 5.4.1 boundary scan register (bsr).............................................................. 53 5.5 device identification register (idr) ....................................................................56 5.5.1 bypass register (byr) .......................................................................... 56 5.5.2 analog port scan register (asr) .......................................................... 57 5.5.3 instruction register (ir) ......................................................................... 58 6.0 test specifications .................................................................................................. 59 6.1 recommendations and specifications ................................................................ 81 7.0 mechanical specifications ................................................................................... 82 7.1 top label markings............................................................................................. 84 8.0 product ordering information ............................................................................. 85 9.0 package information ............................................................................................... 86 figures 1 lxt386 block diagram ......................................................................................... 7 2 lxt386 detailed block diagram ........................................................................... 8 3 lxt386 low-profile quad flat package (lqfp) 100 pin assignments ............... 9 4 lxt386 plastic ball grid array (pbga) 160 ball assignments........................... 10 5 pullup resistor to reset ................................................................................... 23 6 50% ami encoding..............................................................................................27 7 external transmit/receive line circuitry ............................................................ 31 8 jitter attenuator loop.......................................................................................... 33 9 analog loopback ................................................................................................ 34 10 digital loopback.................................................................................................. 34 11 remote loopback ............................................................................................... 35 12 taos data path ................................................................................................. 36 13 taos with analog loopback .............................................................................. 36 14 serial host mode timing ..................................................................................... 42 15 lxt386 jtag architecture ................................................................................. 50 16 jtag state diagram ........................................................................................... 52 17 analog test port application............................................................................... 58 18 transmit clock timing diagram .......................................................................... 65 19 receive clock timing diagram ...........................................................................66 20 jtag timing ....................................................................................................... 67 21 non-multiplexed intel mode read timing ........................................................... 68 22 multiplexed intel read timing............................................................................. 69 23 non-multiplexed intel mode write timing ........................................................... 70 24 multiplexed intel mode write timing ................................................................... 71 25 non-multiplexed motorola mode read timing .................................................... 72 26 multiplexed motorola mode read timing............................................................ 73 27 non-multiplexed motorola mode write timing .................................................... 74 28 multiplexed motorola mode write timin .............................................................. 75 29 serial input timing ..............................................................................................76 30 serial output timing ........................................................................................... 76
datasheet 5 quad t1/e1/j1 transceiver ? lxt386 31 e1, g.703 mask templates................................................................................. 77 32 t1, t1.102 mask templates................................................................................ 78 33 lxt386 jitter tolerance performance ................................................................79 34 jitter transfer performance.................................................................................80 35 output jitter for ctr12/13 applications .............................................................. 81 36 60 plastic ball grid array (pbga) package dimensions .................................... 82 37 100 pin low quad flat packages (lqfp) dimensions ...................................... 83 38 sample lqfp non-rohs package - intel ? lxt386 transceiver ....................... 84 39 sample lqfp rohs package - intel ? lxt386 transceiver...............................84 40 order matrix ........................................................................................................86 tables 1 pin assignments and signal descriptions ...........................................................11 2 line length equalizer inputs............................................................................... 28 3 jitter attenuation specifications .......................................................................... 32 4 operation mode summary ..................................................................................38 5 microprocessor parallel interface selection ........................................................39 6 serial and parallel port register addresses ....................................................... 43 7 register bit names .............................................................................................43 8 id register, id (00h)...........................................................................................44 9 analog loopback register, aloop (01h)..........................................................44 10 remote loopback register, rloop (02h) ........................................................ 45 11 taos enable register, taos (03h) ..................................................................45 12 los status monitor register, los (04h) ...........................................................45 13 dfm status monitor register, dfm (05h) ..........................................................45 14 los interrupt enable register, lie (06h)...........................................................45 15 dfm interrupt enable register, die (07h)..........................................................45 16 los interrupt status register, lis (08h)............................................................46 17 dfm interrupt status register, dis (09h)...........................................................46 18 software reset register, res (0ah)..................................................................46 19 performance monitoring register, mon (0bh)...................................................46 20 digital loopback register, dl (0ch) ..................................................................46 21 los/ais criteria register, lcs (0dh)................................................................46 22 automatic taos select register, ats (0eh).....................................................47 23 global control register, gcr (0fh)................................................................... 47 24 pulse shaping indirect address register, psiad (10h) .....................................48 25 pulse shaping data register, psdat (11h) ......................................................48 26 output enable register, oer (12h) ...................................................................48 27 ais status monitor register, ais (13h) ..............................................................48 28 ais interrupt enable register, aisie (14h) ........................................................49 29 ais interrupt status register, aisis (15h) .........................................................49 30 tap state description .........................................................................................51 31 device identification register (idr) ....................................................................56 32 analog port scan register ? asr.......................................................................57 33 instruction register ? ir......................................................................................58 34 absolute maximum ratings.................................................................................59 35 recommended operating conditions ................................................................. 59 36 dc characteristics ..............................................................................................60 37 e1 transmit transmission characteristics..........................................................61
lxt386 ? quad t1/e1/j1 transceiver 6 datasheet 38 e1 receive transmission characteristics........................................................... 61 39 t1 transmit transmission characteristics.......................................................... 62 40 t1 receive transmission characteristics ........................................................... 63 41 jitter attenuator characteristics .......................................................................... 64 42 analog test port characteristics......................................................................... 65 43 transmit timing characteristics.......................................................................... 65 44 receive timing characteristics...........................................................................66 45 jtag timing characteristics .............................................................................. 67 46 intel mode read timing characteristics ............................................................. 67 47 intel mode write timing characteristics ............................................................. 69 48 motorola bus read timing characteristics ......................................................... 71 49 motorola mode write timing characteristics ...................................................... 73 50 serial i/o timing characteristics......................................................................... 75 51 transformer specifications3 ............................................................................... 76 52 g.703 2.048 mbit/s pulse mask specifications ................................................... 77 53 t1.102 1.544 mbit/s pulse mask specifications.................................................. 77 54 product ordering information .............................................................................. 85 revision history date revision description nov 2005 002 added reduction of hazardous substances package information, starting at section 7.1, ?top label markings? on page 84 . nov 2000 001 initial release
quad t1/e1/j1 transceiver ? lxt386 datasheet 7 1.0 features ? single rail 3.3v supply with 5v tolerant inputs ? low power consumption of 150mw per channel (typical) ? superior crystal-less jitter attenuator ? meets etsi ctr12/13, itu g.736, g.742, g.823 and at&t pub 62411 specifications ? optimized for sonet/sdh applications, meets itu g.783 mapping jitter specification ? constant throughput delay jitter attenuator ? hitless protection switching (hps) for 1 to 1 protection without relays ? hdb3, b8zs, or ami line encoder/decoder ? provides protected monitoring points per itu g.772 ? analog/digital and remote loopback testing functions ? los per itu g.775, ets 300 233 and t1.231 ? 8 bit parallel or 4 wire serial control interface ? hardware and software control modes ? jtag boundary scan test port per ieee 1149.1 ? 160 pbga and 100 pin lqfp packages figure 1. lxt386 block diagram hardw are / softw are control ( j tag i nterface) analog loopback data slicer line driver g.772 monitor data clock pulse mclk los los clock recovery pulse shaper digital loopback remote loopback tpos tclk tneg rpos rclk rneg 0 1 2 3 b8zs / hdb3 decoder b8zs / hdb3 encoder j i tter attenuator rx or tx path j i tter attenuator rx or tx path mode clke loop 0. .3 rtip rring tti p tring jtag serial/ parallel port jasel
lxt386 ? quad t1/e1/j1 transceiver 8 datasheet figure 2. lxt386 detailed block diagram los1 tpos1/tneg1/tclk1 rpos1/rneg1/rclk1 los2 tpos2/tneg2/tclk2 rpos2/rneg2/rclk2 rtip2/rring2 ttip2/tring2 rtip1/rring1 ttip1/tring1 transceiver 2 transceiver 1 transceiver 0 g.772 protected monitoring point los0 rpos0 rclk0 rneg0 tring0 ttip0 a3 - a0 mux hardware / software control (jtag interface) analog loopback data slicer line driver data clock pulse los clock recovery pulse shaper digital loopback remote loopback b8zs / hdb3 decoder b8zs / hdb3 encoder jitter attenuator rx or tx path jitter attenuator rx or tx path jtag serial/ parallel port rtip3 rring3 ttip3 tring3 mclk los3 tpos3 tclk3 tneg3 rpos3 rclk3 rneg3 transceiver 3 mode clke jasel loop 0..7 analog loopback data slicer line driver data clock pulse digital loopback remote loopback b8zs / hdb3 decoder b8zs / hdb3 encoder jitter attenuator rx or tx path jitter attenuator rx or tx path los clock recovery pulse shaper tpos0 tclk0 tneg0 rring0 rtip0
quad t1/e1/j1 transceiver ? lxt386 datasheet 9 2.0 pin assignments and signal description figure 3 shows the pin assignments for lqfp packages. for current package markings, see section 7.1, ?top label markings? on page 84 and the sections that follow. figure 3. lxt386 low-profile quad flat package (lqfp) 100 pin assignments vcc gnd tdo trst tms 75 74 73 72 71 tdi tck vcc vcc gnd gnd tclk2 tpos2 tneg2 rclk2 rpos2 rneg2 los2 tclk3 tpos3 tneg3 rclk3 rpos3 rneg3 los3 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 mot vcc gnd vcc gnd vcc vcc gnd gnd tclk1 tpos1 tneg1 rclk1 rpos1 rneg1 los1 tclk0 tpos0 tneg0 rclk0 rpos0 rneg0 los0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 tvcc0 ttip0 tring0 tgnd0 rtip0 rring0 tgnd1 tring1 ttip1 tvcc1 rring1 rtip1 tvcc2 ttip2 tring2 tgnd2 rtip2 rring2 tgnd3 tring3 ttip3 tvcc3 rring3 rtip3 n/c 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 reset mux cs d7 d6 100 99 98 97 96 d5 d4 d3 d2 d1 d0 a4 a3 a2 a1 a0 clke oe ale ack mode mclk at1 at2 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 r / w ds int lxt386le xx xxxxxx xxxxxxxx part # lot # fpo # rev #
lxt386 ? quad t1/e1/j1 transceiver 10 datasheet figure 4. lxt386 plastic ball grid array (pbga) 160 ball assignments lxt386be (bottom view) n/c n/c n/c tvcc n/c gnd n/c n/c gnd n/c vcc n/c n/c n/c gnd gnd gnd tvcc n/c gnd n/c n/c gnd n/c vcc gnd gnd gnd n/c n/c n/c vcc n/c gnd n/c n/c gnd n/c vcc n/c n/c n/c gnd gnd gnd vcc n/c gnd n/c n/c gnd n/c vcc gnd gnd gnd clke n/c n/c n/c n/c mode mclk tck tdo tdi tms a 4 a 3 a 2 a 1 vcc at 2 gnd gnd a 0 d0 vcc vcc at 1 gnd gnd d1 d2 vcc ale d3 d4 d5 d6 los 2 los 3 los 0 los 1 mux d7 tclk 2 tpos 2 tneg 2 tvcc 2 ttip 2 tgnd 2 rring 2 ttip 1 tgnd 1 rring 1 tvcc 1 tneg 1 tpos 1 tclk 1 rclk 2 rpos 2 rneg 2 tvcc 2 tring 2 tgnd 2 rtip 2 tring 1 tgnd 1 rtip 1 tvcc 1 rneg 1 rpos 1 rclk 1 tclk 3 tpos 3 tneg 3 tvcc 3 ttip 3 tgnd 3 rring 3 ttip 0 tgnd 0 rring 0 tvcc 0 tneg 0 tpos 0 tclk 0 rclk 3 rpos 3 rneg 3 tvcc 3 tring 3 tgnd 3 rtip 3 tring 0 tgnd 0 rtip 0 tvcc 0 rneg 0 rpos 0 rclk 0 ds r / w ack int a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 trst oe mot cs
quad t1/e1/j1 transceiver ? lxt386 datasheet 11 table 1. pin assignments and signal descriptions (sheet 1 of 11) ball # pbga pin # lqfp symbol i/o 1 description e1 78 mclk di master clock . mclk is an independent, free-running reference clock. it?s frequency should be 1.544 mhz for t1 operation and 2.048 mhz for e1 operation. this reference clock is used to generate several internal reference signals: ? timing reference for the integrated clock recovery unit ? timing reference for the integrated digital jitter attenuator ? generation of rclk signal during a loss of signal condition ? reference clock during a blue alarm transmit all ones condition ? reference timing for the parallel processor wait state generation logic if mclk is high, the pll clock recovery circuit is disabled. in this mode, the lxt386 operates as simple data receiver. if mclk is low, the complete receive path is powered down and the output pins rclk, rpos and rneg are switched to tri-state mode. mclk is not required if lxt386 is used as a simple analog front-end without clock recovery and jitter attenuation. note that wait state generation via rdy/ack is not available if mclk is not provided. e2 79 mode di mode select . this pin is used to select the operating mode of the lxt386. in hardware mode, the parallel processor interface is disabled and hardwired pins are used to control configuration and report status. in parallel host mode, the parallel port interface pins are used to control configuration and report status. in serial host mode the serial interface pins: sdi, sdo, sclk and cs are used. for serial host mode, the pin should connected to a resistive divider consisting of two 10 k resistors across v cc and ground. f4 89 a4 di address select . in host mode, this pin is address 4 input pin. in hardware mode this pin must be connected to ground. 1. di: digital input; do: digital output; di/o: digital bidirectional port; ai: analog input; ao: analog output s: power supply; n.c.: not connected. 2. n/c means ?not connected? mode operating mode l hardware mode h parallel host mode vcc/2 serial host mode
lxt386 ? quad t1/e1/j1 transceiver 12 datasheet f3 f2 f1 g3 88 87 86 85 a3 a2 a1 a0 di di di di protected monitoring/address select inputs. hardware mode in hardware mode these pins are used to select a specific port for non intrusive monitoring. during protection monitoring receiver 0 inputs are internally connected to a specific transmit or receive port. receiver 0 routes the data from the selected port to its data and clock recovery circuits. the data on the monitor port can be routed to ttip0/tring0 by activating the remote loopback for channel 0 (tclk0 must be active in order for this operation to take place). in addition, the recovered clock and data can be observed at the rclk0/rpos0/rneg0 outputs. if a0-a3 are low, the lxt386 is configured as a quad line transceiver without monitoring capability. transmitter monitoring is not supported when the respective channel is set to analog loopback mode. host mode in non-multiplexed host mode, these pins function as non-multiplexed address pins. table 1. pin assignments and signal descriptions (sheet 2 of 11) ball # pbga pin # lqfp symbol i/o 1 description 1. di: digital input; do: digital output; di/o: digital bidirectional port; ai: analog input; ao: analog output s: power supply; n.c.: not connected. 2. n/c means ?not connected? a3 a2 a1 a0 selection 0 0 0 0 no protection monitoring 0 0 0 1 receiver 1 0 0 1 0 receiver 2 0 0 1 1 receiver 3 0 1 0 0 reserved 0 1 0 1 reserved 0 1 1 0 reserved 0 1 1 1 reserved 1 0 0 0 no protection monitoring 1 0 0 1 transmitter 1 1 0 1 0 transmitter 2 1 0 1 1 transmitter 3 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved
quad t1/e1/j1 transceiver ? lxt386 datasheet 13 g2 h3 h2 j4 j3 j2 j1 k1 90 91 92 93 94 95 96 97 d0/loop0 d1/loop1 d2/loop2 d3/loop3 d4/dloop0 d5/dloop1 d6/dloop2 d7/dloop3 di/o di/o di/o di/o di/o di/o di/o di/o loopback mode select/parallel data bus . host mode: when a non-multiplexed microprocessor interface is selected, these pins function as a bi-directional 8-bit data port. when a multiplexed microprocessor interface is selected, these pins carry both bi-directional 8-bit data and address inputs a0 -a7. in serial mode, d0-7 should be grounded. hardware mode: in hardware mode, the lxt386 works in normal operation if this pin is left open (unconnected). the lxt386 enters remote loopback mode if loop is low. in this mode, data on tpos and tneg is ignored and data received on rtip and rring is looped around and retransmitted on ttip and tring. note: in data recovery mode, the pulse template cannot be guaranteed while in a remote loopback. the lxt386 enters analog local loopback mode if loop=1 and dloop=0. in this mode, data received on rtip and rring is ignored and data transmitted on ttip and tring is internally looped around and routed back to the receive inputs. the lxt386 enters digital local loopback if loop=1 and dloop=1. in this mode, data received on tclk/tpos/tneg is digitally looped back to rclk/rpos/rneg. note: note: when these inputs are left open, they stay in a high impedance state. therefore, the layout design should not route signals with fast transitions near the loop pins. this practice will minimize capacitive coupling. l1 12 tclk1 di transmit clock. l2 13 tpos1/ tdata1 di di transmit positive data. transmit data. l3 14 tneg1/ ubs1 di di transmit negative data. unipolar/bipolar select. m1 15 rclk1 do receive clock. m2 16 rpos1/ rdata1 do do receive positive data. receive data. m3 17 rneg1/ bpv1 do do receive negative data. bipolar violation detect. k3 18 los1 do loss of signal. table 1. pin assignments and signal descriptions (sheet 3 of 11) ball # pbga pin # lqfp symbol i/o 1 description 1. di: digital input; do: digital output; di/o: digital bidirectional port; ai: analog input; ao: analog output s: power supply; n.c.: not connected. 2. n/c means ?not connected? loop dloop operating mode open x normal mode 0 x remote loopback 1 0 analog local loopback 1 1 digital local loopback
lxt386 ? quad t1/e1/j1 transceiver 14 datasheet n1 19 tclk0 di transmit clock. during normal operation tclk is active, and tpos and tneg are sampled on the falling edge of tclk. if tclk is low, the output drivers enter a low power high z mode. if tclk is high for more than 16 clock cycles the pulse shaping circuit is disabled and the transmit output pulse widths are determined by the tpos and tneg duty cycles. when pulse shaping is disabled, it is possible to overheat and damage the lxt384 device by leaving transmit inputs high continuously. for example a programmable asic might leave all outputs high until it is programmed. to prevent this, clock one of these signals: tpos, tneg, tclk or mclk. another solution is to set one of these signals low: tpos, tneg, tclk, or oe. note that the taos generator uses mclk as a timing reference. in order to assure that the output frequency is within specification limits, mclk must have the applicable stability. n2 20 tpos0/ tdata0 di di transmit positive data. transmit data. transmit negative data. unipolar/bipolar select. bipolar mode : tpos/tneg are active high nrz inputs. tpos indicates the transmission of a positive pulse whereas tneg indicates the transmission of a negative pulse. unipolar mode : when tneg/ubs is pulled high for more than 16 consecutive tclk clock cycles, unipolar i/o is selected. in unipolar mode, b8zs/hdb3 or ami encoding/decoding is determined by the coden pin (hardware mode) or by the coden bit in the gcr register (software mode). tdata is the data input in unipolar i/o mode. n3 21 tneg0/ ubs0 di di table 1. pin assignments and signal descriptions (sheet 4 of 11) ball # pbga pin # lqfp symbol i/o 1 description 1. di: digital input; do: digital output; di/o: digital bidirectional port; ai: analog input; ao: analog output s: power supply; n.c.: not connected. 2. n/c means ?not connected? tclk operating mode clocked normal operation h taos (if mclk supplied) h disable transmit pulse shaping (when mclk is not available) l driver outputs enter tri-state tpos tneg selection 0 0 space 1 0 positive mark 0 1 negative mark 1 1 space
quad t1/e1/j1 transceiver ? lxt386 datasheet 15 p1 22 rclk0 do receive clock. normal mode : this pin provides the recovered clock from the signal received at rtip and rring. under los conditions there is a transition from rclk signal (derived from the recovered data) to mclk signal at the rclk output. data recovery mode : if mclk is high, the clock recovery circuit is disabled and rpos and rneg are internally connected to an exor that is fed to the rclk output for external clock recovery applications. rclk will be in high impedance state if the mclk pin is low. p2 23 rpos0/ rdata0 do do receive positive. receive data. receive negative data. bipolar violation detect. bipolar mode : in clock recovery mode these pins act as active high bipolar non return to zero (nrz) receive signal outputs. a high signal on rpos corresponds to receipt of a positive pulse on rtip/rring. a high signal on rneg corresponds to receipt of a negative pulse on rtip/rring. these signals are valid on the falling or rising edges of rclk depending on the clke input. in data recovery mode these pins act as rz data receiver outputs. the output polarity is selectable with clke (active high output polarity when clke is high and active low polarity when clke is low). rpos and rneg will go to the high impedance state when the mclk pin is low. unipolar mode : in uni-polar mode, the lxt386 asserts bpv high if any in-service line code violation is detected. rdata acts as the receive data output. hardware mode : during a los condition, rpos and rneg will remain active. host mode : rpos and rneg will either remain active or insert ais into the receive path. selection is determined by the raisen bit in the gcr register. p3 24 rneg0/ bpv0 do do k4 25 los0 do loss of signal . los goes high to indicate a loss of signal, i.e. when the incoming signal has no transitions for a specified time interval. the los condition is cleared and the output pin returns to low when the incoming signal has sufficient number of transitions in a specified time interval. see ?loss of signal detector? on page 25 . k2 99 mux di multiplexed/non-multiplexed select. when low the parallel host interface operates in non-multiplexed mode. when high the parallel host interface operates in multiplexed mode. in hardware mode tie this unused input low. n4, p4 26 tvcc0 s transmit driver power supply . power supply pin for the port 0 output driver. tvcc pins can be connected to either a 3.3v or 5v power supply. refer to the transmitter description. table 1. pin assignments and signal descriptions (sheet 5 of 11) ball # pbga pin # lqfp symbol i/o 1 description 1. di: digital input; do: digital output; di/o: digital bidirectional port; ai: analog input; ao: analog output s: power supply; n.c.: not connected. 2. n/c means ?not connected?
lxt386 ? quad t1/e1/j1 transceiver 16 datasheet n5 p5 27 28 ttip0 tring0 ao ao transmit tip. transmit ring. these pins are differential line driver outputs. ttip and tring will be in high impedance state if the tclk pin is low or the oe pin is low. in software mode, ttip and tring can be tristated on a port-by-port basis by writing a ?1? to the oex bit in the output enable register (oer). n6, p6 29 tgnd0 s transmit driver ground . ground pin for the output driver. p7 n7 30 31 rtip0 rring0 ai ai receive tip. receive ring. these pins are the inputs to the differential line receiver. data and clock are recovered and output on the rpos/rneg and rclk pins. l6, m6 32 tgnd1 s transmit driver ground. m5 l5 33 34 tring1 ttip1 ao ao transmit ring. transmit tip. l4, m4 35 tvcc1 s transmit driver power supply. power supply pin for the port 1 output driver. tvcc pins can be connected to either a 3.3v or 5v power supply. refer to the transmitter description. l7 m7 36 37 rring1 rtip1 ai ai receive ring. receive tip. l11, m11 38 tvcc2 s transmit driver power supply. power supply pin for the port 2 output driver. tvcc pins can be connected to either a 3.3v or 5v power supply. refer to the transmitter description. l10 m10 39 40 ttip2 tring2 ao ao transmit tip. transmit ring. l9, m9 41 tgnd2 s transmit driver ground. m8 l8 42 43 rtip2 rring2 ai ai receive tip. receive ring. n9, p9 44 tgnd3 s transmit driver ground. p10 n10 45 46 tring3 ttip3 ao ao transmit ring. transmit tip. n11, p11 47 tvcc3 s transmit driver power supply. power supply pin for the port 3 output driver. tvcc pins can be connected to either a 3.3v or 5v power supply. refer to the transmitter description. n8 p8 48 49 rring3 rtip3 ai ai receive ring. receive tip. k11 51 los3 do loss of signal. p12 52 rneg3/ bpv3 do do receive negative data. bipolar violation detect. p13 53 rpos3/ rdata3 do do receive positive data. receive data. p14 54 rclk3 do receive clock. table 1. pin assignments and signal descriptions (sheet 6 of 11) ball # pbga pin # lqfp symbol i/o 1 description 1. di: digital input; do: digital output; di/o: digital bidirectional port; ai: analog input; ao: analog output s: power supply; n.c.: not connected. 2. n/c means ?not connected?
quad t1/e1/j1 transceiver ? lxt386 datasheet 17 n12 55 tneg3/ ubs3 di di transmit negative data. unipolar/bipolar select. n13 56 tpos3/ tdata3 di di transmit positive data. transmit data. n14 57 tclk3 di transmit clock. k12 58 los2 do loss of signal. m12 59 rneg2/ bpv2 do do receive negative data. bipolar violation detect. m13 60 rpos2/ rdata2 do do receive positive data. receive data. m14 61 rclk2 do receive clock. l12 62 tneg2/ ubs2 di di transmit negative data. unipolar/bipolar select. l13 63 tpos2/ tdata2 di di transmit positive data. transmit data. l14 64 tclk2 di transmit clock. k13 80 int do interrupt. this active low, maskable, open drain output requires an external 10k pull up resistor. if the corresponding interrupt enable bit is enabled, int goes low to flag the host when the lxt386 changes state (see details in the interrupt handling section). the microprocessor int input should be set to level triggering. k14 81 ack / rdy/ sdo do do do data transfer acknowledge (motorola mode). ready (intel mode). serial data output (serial mode). motorola mode a low signal during a databus read operation indicates that the information is valid. a low signal during a write operation acknowledges that a data transfer into the addressed register has been accepted (acknowledge signal).wait states only occur if a write cycle immediately follows a previous read or write cycle (e.g. read modify write). intel mode a high signal acknowledges that a register access operation has been completed (ready signal). a low signal on this pin signals that a data transfer operation is in progress. the pin goes tristate after completion of a bus cycle. serial mode if clke is high, sdo is valid on the rising edge of sclk. if clke is low, sdo is valid on the falling edge of sclk. this pin goes into high z state during a serial port write access. table 1. pin assignments and signal descriptions (sheet 7 of 11) ball # pbga pin # lqfp symbol i/o 1 description 1. di: digital input; do: digital output; di/o: digital bidirectional port; ai: analog input; ao: analog output s: power supply; n.c.: not connected. 2. n/c means ?not connected?
lxt386 ? quad t1/e1/j1 transceiver 18 datasheet j14 3 ds / wr / sdi/ len0 di di di di data strobe (motorola mode). write enable (intel mode). serial data input (serial mode). line length equalizer (hardware mode). host mode this pin acts as data strobe in motorola mode and as write enable in intel mode. in serial mode this pin is used as serial data input. hardware mode this pin determines the shape and amplitude of the transmit pulse. refer to table 2 . j13 2 r / w / rd / len1 di di di read/write (motorola mode). read enable (intel mode). line length equalizer (hardware mode). host mode this pin functions as the read/write signal in motorola mode and as the read enable in intel mode. hardware mode this pin determines the shape and amplitude of the transmit pulse. refer to table 2 . j12 82 ale/ sclk/ as / len2 di di di di address latch enable (host mode). shift clock (serial mode). address strobe (motorola mode). line length equalizer (hardware mode). host mode the address on the multiplexed address/data bus is clocked into the device with the falling edge of ale. in serial host mode this pin acts as serial shift clock. in motorola mode this pin acts a an active low address strobe. hardware mode this pin determines the shape and amplitude of the transmit pulse. refer to table 2 . table 1. pin assignments and signal descriptions (sheet 8 of 11) ball # pbga pin # lqfp symbol i/o 1 description 1. di: digital input; do: digital output; di/o: digital bidirectional port; ai: analog input; ao: analog output s: power supply; n.c.: not connected. 2. n/c means ?not connected?
quad t1/e1/j1 transceiver ? lxt386 datasheet 19 j11 98 cs / jasel di di chip select/jitter attenuator select. host mode this active low input is used to access the serial/parallel interface. for each read or write operation, cs must transition from high to low, and remain low. hardware mode this input determines the jitter attenuator position in the data path: h12 1 mot /intl/ coden di di motorola/intel/codec enable select. host mode: when low, the host interface is configured for motorola microcontrollers. when high, the host interface is configured for intel microcontrollers. hardware mode: this pin determines the line encode/decode selection when in un- ipolar mode: when low, b8zs/hdb3 encoders/decoders are enabled for t1/e1 respectively. when high, enables ami encoder/decoder (transparent mode). g13 76 at2 ao jtag analog output test port 2. h13 77 at1 ai jtag analog input test port 1. g12 72 trst jtag controller reset. input is used to reset the jtag controller. trst is pulled up internally and may be left disconnected. f11 71 tms di jtag test mode select. used to control the test logic state machine. sampled on rising edge of tck. tms is pulled up internally and may be left disconnected. f14 69 tck di jtag clock. clock input for jtag. connect to gnd when not used. f13 73 tdo do jtag data output. test data output for jtag. used for reading all serial configuration and test data from internal test logic. updated on falling edge of tck. f12 70 tdi di jtag data input . test data input for jtag. used for loading serial instructions and data into internal test logic. sampled on rising edge of tck. tdi is pulled up internally and may be left disconnected. e14 83 oe di output driver enable. if this pin is asserted low all analog driver outputs immediately enter a high impedance mode to support redundancy applications without external mechanical relays. all other internal circuitry stays active. in software mode, ttip and tring can be tristated on a port-by-port basis by writing a ?1? to the oex bit in the output enable register (oer). table 1. pin assignments and signal descriptions (sheet 9 of 11) ball # pbga pin # lqfp symbol i/o 1 description 1. di: digital input; do: digital output; di/o: digital bidirectional port; ai: analog input; ao: analog output s: power supply; n.c.: not connected. 2. n/c means ?not connected? jasel ja position l transmit path h receive path z disabled
lxt386 ? quad t1/e1/j1 transceiver 20 datasheet e13 84 clke di clock edge select. in clock recovery mode, setting clke high causes rdata or rpos and rneg to be valid on the falling edge of rclk and sdo to be valid on the rising edge of sclk. setting clke low makes rdata or rpos and rneg to be valid on the rising edge of rclk and sdo to be valid on the falling edge of sclk. in data recovery mode, rdata or rpos/rneg are active high output polarity when clke is high and active low polarity when clke is low. n/c 2 100 reset di reset input. (added in revision b1) in either hardware mode or software mode, setting reset low will begin to initialize the lxt386 and freeze the device until set high. one microsecond after setting reset high, initialization will complete and the lxt386 will be ready for normal operation. for revision b1 only, the device requires a pull up resistor to vcc at this pin between 1 and 10 kohms in value. it is not necessary to retain the pull up resistor for any other revision. please refer to the section on reset operation for more information. the bga package does not have this pin feature. a6, a9 b: 1, 2, 3, 6, 9, 12, 13, 14 c6, c9 d: 1, 2, 3, 6, 9, 12, 13, 14 g4, g11 h4, h11 5, 7, 10, 11, 65, 66, 74 gnd s power supply ground. connect all pins to power supply ground. table 1. pin assignments and signal descriptions (sheet 10 of 11) ball # pbga pin # lqfp symbol i/o 1 description 1. di: digital input; do: digital output; di/o: digital bidirectional port; ai: analog input; ao: analog output s: power supply; n.c.: not connected. 2. n/c means ?not connected? clke rpos/rneg sdo low high sclk sclk rclk rclk
quad t1/e1/j1 transceiver ? lxt386 datasheet 21 a4, b4, c4, c11, d4, d11, g1, g14, h1, h14 4, 6, 8, 9, 67, 68, 75, vcc s power supply. connect all pins to +3.3 volt power supply. a11, b11 - tvcc s transmit driver power supply . power supply pins for the output drivers. tvcc pins can be connected to either a 3.3v or 5v power supply. refer to ?transmitter? on page 27 for details. a: 1, 2, 3, 5, 7, 10, 12, 13, 14 b: 7, 8, 10 c: 1, 2, 3, 5, 7, 8, 10, 12, 13, 14 d: 5, 7, 8, 10 e: 3, 4, 11, 12 50 n/c nc not connected. these pins must be left open for normal operation. table 1. pin assignments and signal descriptions (sheet 11 of 11) ball # pbga pin # lqfp symbol i/o 1 description 1. di: digital input; do: digital output; di/o: digital bidirectional port; ai: analog input; ao: analog output s: power supply; n.c.: not connected. 2. n/c means ?not connected?
lxt386 ? quad t1/e1/j1 transceiver 22 datasheet 3.0 functional description figure 1 is a simplified block diagram of the lxt386. the lxt386 is a fully integrated quad line interface unit designed for t1 1.544 mbps and e1 2.048 mbps short haul applications. each transceiver front end interfaces with four lines, one pair for transmit, one pair for receive. these two lines comprise a digital data loop for full duplex transmission. the lxt386 can be controlled through hard-wired pins or by a microprocessor through a serial or parallel interface (host mode). the transmitter timing reference is tclk, and the receiver reference clock is mclk. the lxt386 is designed to operate without any reference clock when used as an analog front-end (line driver and data recovery). mclk is mandatory if the on chip clock recovery capability is used. all four clock recovery circuits share the same reference clock defined by the mclk input signal. 3.1 initialization during power up, the transceiver remains static until the power supply reaches approximately 60% of vcc. during power-up, an internal reset sets all registers to their default values and resets the status and state machines for the los.
quad t1/e1/j1 transceiver ? lxt386 datasheet 23 3.1.1 reset operation in revision b1, no connect pin 100 was converted to the reset pin. only revision b1 requires a pull up resistor to vcc at pin 100, the pull up resistor is unnecessary for all other revisions. figure 4 shows the connections needed for revision b1 only. note: the bga package does not have a reset pin. there are two methods of resetting the lxt386: 1. override reset - setting the reset pin low in either hardware mode or host mode. until the reset pin returns high, the lxt386 remains frozen and will not function. once the reset pin has returned high, the lxt386 will operaate normally. override reset changes all the internal registers to their default values. 2. software reset - writing to the res reset register initiates a 1microsecond reset cycle, except in intel non-multiplexed mode. in intel non-multiplexed mode, the reset cycle takes 2 microseconds. please refer to host mode section for more information. this operation changes all lxt386 registers to their default values. figure 5. pullup resistor to reset lxt386le vcc 1k 100 reset
lxt386 ? quad t1/e1/j1 transceiver 24 datasheet 3.2 receiver the four receivers in the lxt386 are identical. the following paragraphs describe the operation of one. the twisted-pair input is received via a 1:2 step down transformer. positive pulses are received at rtip, negative pulses at rring. recovered data is output at rpos and rneg in the bipolar mode and at rdata in the unipolar mode. the recovered clock is output at rclk. rpos/rneg validation relative to rclk is pin selectable (clke). the receive signal is processed through the peak detector and data slicers. the peak detector samples the received signal and determines its maximum value. a percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. for dsx-1 applications (line length inputs len2-0 from 011 to 111) the threshold is set to 70% (typical) of the peak value. this threshold is maintained above the specified level for up to 15 successive zeros over the range of specified operating conditions. for e1 applications (len2-0 = 000), the threshold is 50% (typical). the receiver is capable of accurately recovering signals with up to 12 db of attenuation (from 2.4 v), corresponding to a received signal level of approximately 500 mv. maximum line length is 1500 feet of abam cable (approximately 6 db of attenuation). regardless of received signal level, the peak detectors are held above a minimum level of 0.150 v (typical) to provide immunity from impulsive noise. after processing through the data slicers, the received signal goes to the data and timing recovery section. the data and timing recovery circuits provide an input jitter tolerance better than required by pub 62411 and itu g.823, as shown in test specifications, figure 33 . depending on the options selected, recovered clock and data signals may be routed through the jitter attenuator, through the b8zs/hdb3/ami decoder, and may be output to the framer as either bipolar or unipolar data.
quad t1/e1/j1 transceiver ? lxt386 datasheet 25 3.2.1 loss of signal detector the loss of signal detector in the lxt386 uses a dedicated analog and digital loss of signal detection circuit. it is independent of its internal data slicer comparators and complies to the latest itu g.775 and ansi t1.231 recommendations. under software control, the detector can be configured to comply to the etsi ets 300 233 specification ( lacs register). in hardware mode, the lxt386 supports los per g.775 for e1 and ansi t1.231 for t1 operation. the receiver monitor loads a digital counter at the rclk frequency. the counter is incremented each time a zero is received, and reset to zero each time a one (mark) is received. depending on the operation mode, a certain number of consecutive zeros sets the los signal. the recovered clock is replaced by mclk at the rclk output with a minimum amount of phase errors. mclk is required for receive operation. when the los condition is cleared, the los flag is reset and another transition replaces mclk with the recove red clock at rclk. rpos/rneg will reflect the data content at the receiver input during the entire los detection period for that channel. 3.2.1.1 e1 mode in g.775 mode a loss of signal is detected if the signal is below 200mv (typical) for 32 consecutive pulse intervals. when the received signal reaches 12.5% ones density (4 marks in a sliding 32-bit period) with no more than 15 consecutive zeros and the signal level exceeds 250mv (typical), the los flag is reset and another transition replaces mclk with the recovered clock at rclk. in etsi 300 233 mode, a loss of signal is detected if the signal is below 200mv for 2048 consecutive intervals (1 ms). the los condition is cleared and the output pin returns to low when the incoming signal has transitions when the signal level is equal or greater than 250mv for more than 32 consecutive pulse intervals. this mode is activated by setting the lacs register bit to one. if it is necessary to use ais with los, see errata 10.3 for a way to implement this. 3.2.1.2 t1 mode the t1.231 los detection criteria is employed. los is detected if the signal is below 200mv for 175 contiguous pulse positions. the los condition is terminated upon detecting an average pulse density of 12.5% over a period of 175 contiguous pulse positions starting with the receipt of a pulse. the incoming signal is considered to have transitions when the signal level is equal or greater than 250mv. 3.2.1.3 data recovery mode in data recovery mode the los digital timing is derived from a internal self timed circuit. rpos/ rneg stay active during loss of signal. the analog los detector complies with itu-g.775 recommendation. the lxt386 monitors the incoming signal amplitude. any signal below 200mv for more than 30 s (typical) will assert the corresponding los pin. the los condition is cleared when the signal amplitude rises above 250mv. the lxt386 requires more than 10 and less than 255 bit periods to declare a los condition in accordance to itu g.775.
lxt386 ? quad t1/e1/j1 transceiver 26 datasheet 3.2.2 alarm indication signal (ais) detection the ais detection is performed by the receiver independent of any loopback mode. this feature is available in host mode only. because there is no clock in data recovery mode, ais detection will not work in that mode. ais requires mclk to have clock applied, since this function depends on the clock to count the number of ones in an interval. 3.2.2.1 e1 mode one detection mode suitable for both etsi and itu is available when the lacs register bits are cleared to zero. if the lacs register bit is set to one, see errata 10.3 to implement this: etsi ets300233 and g.775 detection the ais condition is declared when the received data stream contains less than 3 zeros within a period of 512 bits. the ais condition is cleared when 3 or more zeros within 512 bits are detected. 3.2.2.2 t1 mode ansi t1.231 detection is employed. the ais condition is declared when less than 9 zeros are detected in any string of 8192 bits. this corresponds to a 99.9% ones density over a period of 5.3ms. the ais condition is cleared when the received signal contains 9 or more zeros in any string of 8192 bits. 3.2.3 in service code violation monitoring in unipolar i/o mode with hdb3/b8zs decoding, the lxt386 reports bipolar violations on rneg/bpv for one rclk period for every hdb3/b8zs code violation that is not part of the zero code substitution rules. in ami mode, all bipolar violations (two consecutive pulses with the same polarity) are reported at the bpv output.
quad t1/e1/j1 transceiver ? lxt386 datasheet 27 3.3 transmitter the four low power transmitters of the lxt386 are identical. transmit data is clocked serially into the device at tpos/tneg in the bipolar mode or at tdata in the unipolar mode. the transmit clock (tclk) supplies the input synchronization. unipolar i/o and hdb3/b8zs/ami encoding/decoding is selected by pulling tneg high for more than 16 consecutive tclk clock cycles. the transmitter samples tpos/tneg or tdata inputs on the falling edge of tclk. refer to the test specifications section for mclk and tclk timing characteristics. if tclk is not supplied, the transmitter remains powered down and the ttip/ tring outputs are held in a high z state. in addition, fast output tristatability is also available through the oe pin (all ports) and/or the port?s oex bit in the output enable register (oer). zero suppression is available only in unipolar mode. the two zero-suppression types are b8zs, used in t1 environments, and hdb3, used in e1 environments. the scheme selected depends on whether the device is set for t1 or e1 operation (determined by len2-0 pulse shaping settings). the lxt386 also supports ami line coding/decoding as shown in figure 6 . in hardware mode, ami coding/decoding is selected by the coden pin. in host mode, ami coding/decoding is selected by bit 4 in the gcr (global control register). each output driver is supplied by a separate power supply (tvcc and tgnd). the transmit pulse shaper is bypassed if no mclk is supplied while tclk is pulled high. in this case tpos and tneg control the pulse width and polarity on ttip and tring. with mclk supplied and tclk pulled high the driver enters taos (transmit all ones pattern). note that the taos generator uses mclk as a timing reference. in order to assure that the output frequency is within specification limits, mclk must have the applicable stability.taos is inhibited during remote loopback. figure 6. 50% ami encoding ttip tring 1 0 1 bit cell
lxt386 ? quad t1/e1/j1 transceiver 28 datasheet 3.3.1 transmit pulse shaping the transmitted pulse shape is internally generated using a high speed d/a converter. shaped pulses are further applied to the line driver for transmission onto the line at ttip and tring. the line driver provides a constant low output impedance regardless of whether it is driving marks, spaces or if it is in transition. this well controlled dynamic impedance provides excellent return loss when used with external precision resistors ( 1% accuracy) in series with the transformer. 3.3.1.1 hardware mode in hardware mode, pins len0-2 determine the pulse shaping as described in table 2 . the len settings also determine whether the operating mode is t1 or e1. note that in t1 operation mode, all four ports will share the same pulse shaping setting. independent pulse shaping for each channel is available in host mode 3.3.1.2 host mode in host mode, the contents of the pulse shaping data register (psdat) determines the shape of pulse output at ttip/tring. refer to table 24 and table 25 . . table 2. line length equalizer inputs len2 len1 len0 line length 1 cable loss 2 operation mode 011 0 - 133 ft. abam 133 - 266 ft. abam 266 - 399 ft. abam 399 - 533 ft. abam 533 - 655 ft. abam 0.6 db 1.2 db 1.8 db 2.4 db 3.0 db t1 100 101 110 111 0 0 0 e1 g.703, 75 coaxial cable and 120 twisted pair cable. e1 1. line length from lxt386 to dsx-1 cross-connect point. 2. maximum cable loss at 772khz.
quad t1/e1/j1 transceiver ? lxt386 datasheet 29 3.3.2 transmit pulse shaping the transmitted pulse shape is internally generated using a high speed d/a converter. shaped pulses are further applied to the line driver for transmission onto the line at ttip and tring. the line driver provides a constant low output impedance regardless of whether it is driving marks. 3.3.2.1 output driver power supply the output driver power supply (tvcc pins) can be either 3.3v or 5v nominal. when tvcc=5v, lxt386 drives both e1 (75 /120 ) and t1 100 lines through a 1:2 transformer and 11 / 9.1 series resistors. when tvcc=3.3v, the lxt386 drives e1 (75 /120 ) lines through a 1:2 transformer and 11 series resistor. a configuration with a 1:2 transformer and without series resistors should be used to drive t1 100 lines. removing the series resistors for t1 applications with tvcc=3.3v, improves the power consumption of the device. see table 35 . on the other hand, series resistors in the transmit configuration improve the transmit return loss performance. good transmit return loss performance minimizes reflections in harsh cable environments. in addition, series resistors provide protection against surges coupled to the device. the resistors should be used in systems requiring protection switching without external relays. please refer to figure 7 for the recommended external line circuitry. 3.3.2.2 power sequencing for the lxt384, we recommend sequencing tvcc first then vcc second or at the same time as tvcc to prevent excessive current draw.
lxt386 ? quad t1/e1/j1 transceiver 30 datasheet 3.4 driver failure monitor the lxt386 transceiver incorporates an internal power driver failure monitor (dfm) in parallel with ttip and tring that is capable of detecting secondary shorts without cable. dfm is available only in configurations with no transmit series resistors (t1 mode with tvcc=3.3v). this feature is available in the serial and parallel host modes but not available in the hardware mode of operation. a capacitor, charged via a measure of the driver output current and discharged by a measure of the maximum allowable current, is used to detect a secondary short failure. secondary shorted lines draw excess current, overcharging the cap. when the capacitor charge deviates outside the nominal charge window, a driver short circuit fail (dfm) is reported in the respective register by setting an interrupt. during a long string of spaces, a short-induced overcharge eventually bleeds off, clearing the dfm flag. note that unterminated lines of adequate length ( /4) may effectively behave as short-circuits as seen by the driver and therefore trigger the dfm. under these circumstances, the alarm should be disabled. in addition, lxt386 features output driver short-circuit protection. when the output current exceeds 100 ma, lxt386 limits the driver?s output voltage to avoid damage. 3.5 line protection figure 7 on page 31 shows recommended line interface circuitry. in the receive side, the 1 k series resistors protect the receiver against current surges coupled into the device. due to the high receiver impedance (70 k typical) the resistors do not affect the receiver sensitivity. in the transmit side, the schottky diodes d1-d4 protect the output driver.while not mandatory for normal operation, these protection elements are strongly recommended to improve the design robustness.
quad t1/e1/j1 transceiver ? lxt386 datasheet 31 figure 7. external transmit/receive line circuitry 0.1 f tvcc r t r t 1:2 ttip tring tvcc tgnd rtip rring r r r r 0.22 f 1:2 68 f 1 1 common decoupling capacitor for all tvcc and tgnd pins. tvcc d1 d2 tvcc d3 d4 560pf 2 1k 1k rx line tx line vcc gnd lxt386 (one channel) 0.1 f 3.3v 3 3 refer to transformer specifications table for transformer specifications. tvcc tvs1 2 typical value. adjust for actual board parasitics to obtain optimum return loss. component e1 75 coax e1 120 twisted pair t1 100 twisted pair tvcc = 5v t1 100 twisted pair tvcc = 3.3v r t 11 1% 11 1% 9.1 1% 0 r r 9.31 1% 15.0 1% 12.4 1% 12.4 1% d1 - d4 international rectifier.............11dq04 or 10bq060 motorola.......................................mbr0540t1 tvs1 sgs-thomson..............smlvt 3v3 3.3v transient voltage suppressor (tvcc=3.3v) semtech.......................smcj5.0ac 5.0v transient voltage suppressor (tvcc=5.0v) 0.1 f tvcc r t r t 1:2 ttip tring tvcc tgnd rtip rring r r r r 0.22 f 1:2 68 f 1 1 common decoupling capacitor for all tvcc and tgnd pins. tvcc d1 d2 tvcc d3 d4 560pf 2 1k 1k rx line tx line vcc gnd lxt386 (one channel) 0.1 f 3.3v 3 3 refer to transformer specifications table for transformer specifications. tvcc tvs1 2 typical value. adjust for actual board parasitics to obtain optimum return loss.
lxt386 ? quad t1/e1/j1 transceiver 32 datasheet 3.6 jitter attenuation a digital jitter attenuation loop (jal) combined with a fifo provides jitter attenuation. the jal is internal and requires no external crystal nor high-frequency (higher than line rate) reference clock. in host mode, the global control register (gcr) determines whether the jal is positioned in the receive or transmit path. in hardware mode, the jal position is determined by the jasel pin. the fifo is a 32 x 2-bit or 64 x 2-bit register (selected by the fifo64 bit in the gcr). data is clocked into the fifo with the associated clock signal (tclk or rclk), and clocked out of the fifo with the dejittered jal clock. see figure 8 . when the fifo is within two bits of overflowing or underflowing, the fifo adjusts the output clock by 1/8 of a bit period. the jitter attenuator produces a constant delay of 17 or 33 bits in the associated path (refer to test specifications). this feature can be used for hitless switching applications. this advanced digital jitter attenuator meets latest jitter attenuation specifications. see table 3 . under software control, the low limit jitter attenuator corner frequency depends on fifo length and the jacf bit setting (this bit is in the gcr register). in hardware mode, the fifo length is fixed to 64 bits. the corner frequency is fixed to 6 hz for t1 mode and 3.5 hz for e1 mode. table 3. jitter attenuation specifications t1 e1 at&t pub 62411 itu-t g.736 gr-253-core 1 itu-t g.742 3 tr-tsy-000009 2 itu-t g.783 4 etsi ctr12/13 bapt 220 1. category i, r5-203. 2. section 4.6.3. 3. section 6.2 when used with the sxt6234 e2-e1 mux/demux. 4. section 6.2.3.3 combined jitter when used with the sxt6251 21e1 mapper.
quad t1/e1/j1 transceiver ? lxt386 datasheet 33 figure 8. jitter attenuator loop fifo dpll in ck out ck tpos rposi tneg rnegi tclk rclki jasel0-1 tposo rpos tnego rneg tclk rclk jasel0-1 fifo64 jacf mclk gcr control bits x 32 in out
lxt386 ? quad t1/e1/j1 transceiver 34 datasheet 3.7 loopbacks the lxt386 offers three loopback modes for diagnostic purposes. in hardware mode, the loopback mode is selected with the loopn pins. in software mode, the aloop, dloop and rloop registers are employed. 3.7.1 analog loopback when selected, the transmitter outputs (ttip & tring) are connected internally to the receiver inputs (rtip & rring) as shown in figure 9 . data and clock are output at rclk, rpos & rneg pins for the corresponding transceiver. note that signals on the rtip & rring pins are ignored during analog loopback. 3.7.2 digital loopback the digital loopback function is available in software and hardware mode. when selected, the transmit clock and data inputs (tclk, tpos & tneg) are looped back and output on the rclk, rpos & rneg pins ( figure 10 ). the data presented on tclk, tpos & tneg is also output on the ttip & tring pins. note that signals on the rtip & rring pins are ignored during digital loopback. figure 9. analog loopback timing & control timing recovery ttip tring rtip rring hdb3/b8zs encoder* rclk rpos rneg tclk tpos tneg hdb3/b8zs decoder* * if enabled ja* ja* figure 10. digital loopback timing & control timing recovery ttip tring rtip rring rclk rpos rneg tclk tpos tneg * if enabled ja* ja* hdb3/b8zs encoder* hdb3/b8zs decoder*
quad t1/e1/j1 transceiver ? lxt386 datasheet 35 3.7.3 remote loopback during remote loopback ( figure 11 ) the rclk, rpos & rneg outputs routed to the transmit circuits and output on the ttip & tring pins. note that input signals on the tclk, tpos & tneg pins are ignored during remote loopback. note: in data recovery mode, the pulse template cannot be guaranteed while in a remote loopback. figure 11. remote loopback tclk tpos tneg ttip tring rtip rring * if enabled rclk rpos rneg timing & control timing recovery ja* hdb3/b8zs encoder* hdb3/b8zs decoder* ja*
lxt386 ? quad t1/e1/j1 transceiver 36 datasheet 3.7.4 transmit all ones (taos) in hardware mode, the taos mode is set by pulling tclk high for more than 16 mclk cycles. in software mode, taos mode is set by asserting the corresponding bit in the taos register. in addition, automatic ats insertion (in case of los) may be set using the ats register. note: the taos generator uses mclk as a timing reference, therefore taos doesn?t work in data recovery mode. in order to assure that the output frequency is within specification limits, mclk must have the applicable stability. dloop does not function with taos active. figure 12. taos data path figure 13. taos with analog loopback taos mode tclk tpos tneg rclk rpos rneg ttip tring rtip rring * if enabled mclk (all 1's) timing & control timing recovery ja* hdb3/b8zs encoder* hdb3/b8zs decoder* ttip tring rtip rring rclk rpos rneg tclk tpos tneg * if enabled mclk taos mode timing & control timing recovery ja* hdb3/b8zs encoder* hdb3/b8zs decoder* (all 1's)
quad t1/e1/j1 transceiver ? lxt386 datasheet 37 3.8 g.772 performance monitoring the lxt386 can be configured as a quad line interface unit with all channels working as regular transceivers. in applications using only three channels, the fourth channel can be configured to monitor any of the remaining channels inputs or outputs. the monitoring is non-intrusive per itu- t g.772. figure 2 on page 8 illustrates this concept. the monitored line signal (input or output) goes through channel 0 clock and data recovery. the signal can be observed digitally at the rclk/rpos/rneg outputs. this feature can also be used to create timing interfaces derived from an e1 or t1 signal. in addition, channel 0 can be configured to a remote loopback while in monitoring mode (tclk0 must be active in order for this operation to take place). this will output the same data as in the signal being monitored at the channel 0 output (ttip/tring). the output signal can then be connected to a standard test equipment with a t1/e1 electrical interface for monitoring purposes (non-intrusive monitoring). 3.9 hitless protection switching (hps) the lxt386 transceivers include an output driver tristatability feature for t1/e1 redundancy applications. this feature greatly reduces the cost of implementing redundancy protection by eliminating external relays. please refer to application note 119 for guidelines for implementing redundancy systems for both t1 and e1 operation using the lxt380/1/4/6.
lxt386 ? quad t1/e1/j1 transceiver 38 datasheet 3.10 operation mode summary table 4 lists summarizes all lxt386 hardware settings and corresponding operating modes. 3.11 interfacing with 5v logic the lxt386 can interface directly with 5v logic. the internal input pads are tolerant to 5v outputs from ttl and cmos family devices. table 4. operation mode summary mclk tclk loop 1 receive mode transmit mode loopback clocked clocked open data/clock recovery pulse shaping on no loopback clocked clocked l data/clock recovery pulse shaping on remote loopback clocked clocked h data/clock recovery pulse shaping on analog loopback clocked l open data/clock recovery power down no loopback clocked l l data/clock recovery power down no effect on op. clocked l h data/clock recovery power down no analog loopback clocked h open data/clock recovery transmit all ones no loopback clocked h l data/clock recovery pulse shaping on remote loopback clocked h h data/clock recovery transmit all ones no effect on op. l clocked open power down pulse shaping on no loopback l clocked l power down pulse shaping on no remote loopback l clocked h power down pulse shaping on no effect on op. l h open power down pulse shaping off no loopback l h l power down pulse shaping off no remote loop l h h power down pulse shaping off no effect on op. l l x power down power down no loopback h clocked open data recovery pulse shaping on no loopback h clocked l data recovery pulse shaping off remote loopback h clocked h data recovery pulse shaping on analog loopback h l open data recovery power down no loopback h l l data recovery pulse shaping off remote loopback h h open data recovery pulse shaping off no loopback h h l data recovery pulse shaping off remote loopback h h h data recovery pulse shaping off analog loopback 1. hardware mode only.
quad t1/e1/j1 transceiver ? lxt386 datasheet 39 3.12 parallel host interface the lxt386 incorporates a highly flexible 8-bit parallel microprocessor interface. the interface is generic and is designed to support both non-multiplexed and multiplexed address/data bus systems for motorola and intel bus topologies. two pins (mux and mot /intl) select four different operating modes as shown in table 5 . the interface includes an address bus (a4 - a0) and a data bus (d7 - d0) for non-multiplexed operation and an 8-bit address/data bus for multiplexed operation. wr , rd , r/w , cs , ale, ds , int and rdy/ack are used as control signals. a significant enhancement is an internal wait-state generator that controls an intel and motorola compatible handshake output signal (rdy/ack ). in motorola mode ack low signals valid information is on the data bus. during a write cycle a low signal acknowledges the acceptance of the write data. in intel mode rdy high signals to the controlling processor that the bus cycle can be completed. while low the microprocessor must insert wait states. this allows the lxt386 to interface with wait-state capable micro controllers, independent of the processor bus speed. to activate this function a reference clock is required on the mclk pin. there is one exception to write cycle timing for intel non-multiplexed mode: register 0ah, the reset register. because of timing issues, the rdy line remains high after the first part of the cycle is done, not signalling write cycle completion with another transition low. in this mode, add 2 microseconds of delay, overall 3 microseconds from cs low to end of cycle, to allow the reset cycle to completely initialize the device before proceeding. an additional active low interrupt output signal indicates alarm conditions like los and dfm to the microprocessor. the lxt386 has a 5 bit address bus and provides 18 user accessible 8-bit registers for configuration, alarm monitoring and control of the chip. table 5. microprocessor parallel interface selection mux mot /intl operating mode low low motorola non-multiplexed low high intel non-multiplexed high low motorola multiplexed high high intel multiplexed
lxt386 ? quad t1/e1/j1 transceiver 40 datasheet 3.12.1 motorola interface the motorola interface is selected by asserting the mot /intl pin low. in non-multiplexed mode the falling edge of ds is used to latch the address information on the address bus. in multiplexed operation the address on the multiplexed address data bus is latched into the device with the falling edge of as . in non-multiplexed mode, as should be pulled high. the r/w signal indicates the direction of the data transfer. the ds signal is the timing reference for all data transfers and typically has a duty cycle of 50%. a read cycle is indicated by asserting r/ w high with a falling edge on ds . a write cycle is indicated by asserting r/w low with a rising edge on ds . both cycles require the cs signal to be low and the address pins to be actively driven by the microprocessor. note that cs and ds can be connected together in motorola mode. in a write cycle the data bus is driven by the microprocessor. in a read cycle the bus is driven by the lxt386. 3.12.2 intel interface the intel interface is selected by asserting the mot /intl pin high. the lxt386 supports non- multiplexed interfaces with separate address and data pins when mux is asserted low, and multiplexed interfaces when mux is asserted high. the address is latched in on the falling edge of ale. in non-multiplexed mode, ale should be pulled high. r/w is used as the rd signal and ds is used as the wr signal. a read cycle is indicated to the lxt386 when the processor asserts rd low while the wr signal is held high. a write operation is indicated to the lxt386 by asserting wr low while the rd signal is held high. both cycles require the cs signal to be low.
quad t1/e1/j1 transceiver ? lxt386 datasheet 41 3.13 interrupt handling interrupt sources there are three interrupt sources: 1. status change in the loss of signal (los) status register (04h). the lxt386?s analog/digital loss of signal processor continuously monitors the receiver signal and updates the specific los status bit to indicate presence or absence of a los condition. 2. status change in the driver failure monitoring (dfm) status register (05h). the lxt386?s smart power driver circuit continuously monitors the output drivers signal and updates the specific dfm status bit to indicate presence or absence of a secondary driver short circuit condition. 3. status change in the alarm indication signal (ais) status register (13h).the lxt386?s receiver monitors the incoming data stream and updates the specific ais status bit to indicate presence or absence of a ais condition. 3.13.1 interrupt enable the lxt386 provides a latched interrupt output (int ). an interrupt occurs any time there is a transition on any enabled bit in the status register. registers 06h, 07h and 14h are the los, dfm and ais interrupt enable registers (respectively). writing a logic ?1? into the mask register will enable the respective bit in the respective interrupt status register to generate an interrupt. the power-on default value is all zeroes. the setting of the interrupt enable bit does not affect the operation of the status registers. registers 08h, 09h and 15h are the los, dfm and ais (respectively) interrupt status registers. when there is a transition on any enabled bit in a status register, the associated bit of the interrupt status register is set and an interrupt is generated (if one is not already pending). when an interrupt occurs, the int pin is asserted low. the output stage of the int pin consists only of a pull-down device; an external pull-up resistor of approximately 10k ohm is required to support wired-or operation. 3.13.2 interrupt clear when an interrupt occurs, the interrupt service routine (isr) should read the interrupt status registers (08h, 09h and 15h) to identify the interrupt source. reading the interrupt status register clears the ?sticky? bit set by the interrupt. automatically clearing the register prepares it for the next interrupt. the isr should then read the corresponding status monitor register to obtain the current status of the device. note that there are three status monitor registers: the los (04h), the dfm (05h) and the ais (013h). reading either status monitors register will clear its corresponding interrupts on the rising edge of the read or data strobe. when all pending interrupts are cleared, the int pin goes high.
lxt386 ? quad t1/e1/j1 transceiver 42 datasheet 3.14 serial host mode the lxt386 operates in serial host mode when the mode pin is tied to vcc 2. figure 14 shows the sio data structure. the registers are accessible through a 16 bit word: an 8bit command/ address byte (bits r/w and a1-a7) and a subsequent 8bit data byte (bits d0-7). bit r/w determines whether a read or a write operation occurs. bits a5-0 in the command/address byte address specific registers (the address decoder ignores bits a7-6). the data byte depends on both the value of bit r/w and the address of the register as set in the command/address byte. figure 14. serial host mode timing cs sclk address/command byte input data byte r/w a1 a2 a3 a4 a5 a6 a7 d0 d1 d2 d3 d4 d5 d6 d7 sdi sdo - remains high z r/w = 1: read from the lxt386 x = don?t care x x sdo is driven if r/w = 1 r/w = 0: write to the lxt386
quad t1/e1/j1 transceiver ? lxt386 datasheet 43 4.0 register descriptions table 6. serial and parallel port register addresses name symbol address mode serial port a7-a1 parallel port a7-a0 id register id xx00000 xxx00000 r analog loopback aloop xx00001 xxx00001 r/w remote loopback rloop xx00010 xxx00010 r/w taos enable taos xx00011 xxx00011 r/w los status monitor los xx00100 xxx00100 r dfm status monitor dfm xx00101 xxx00101 r los interrupt enable lie xx00110 xxx00110 r/w dfm interrupt enable die xx00111 xxx00111 r/w los interrupt status lis xx01000 xxx01000 r dfm interrupt status dis xx01001 xxx01001 r software reset register res xx01010 xxx01010 r/w performance monitoring mon xx01011 xxx01011 r/w digital loopback dl xx01100 xxx01100 r/w los/ais criteria selection losc xx01101 xxx01101 r/w automatic taos select ats xx01110 xxx01110 r/w global control r egister gcr xx01111 xxx01111 r/w pulse shaping indirect address register psiad xx10000 xxx10000 r/w pulse shaping data register psdat xx10001 xxx10001 r/w output enable register oer xx10010 xxx10010 r/w ais status register ais xx10011 xxx10011 r ais interrupt enable aisie xx10100 xxx10100 r/w ais interrupt status aisis xx10101 xxx10101 r table 7. register bit names register bit name symrw76543 2 1 0 id register id r id7 id6 id5 id4 id3 id2 id1 id0 analog loopbackaloopr/w----al3al2al1al0 remote loopbackrloopr/w----rl3rl2rl1rl0 taos enable taosr/w----taos3taos2taos1taos0
lxt386 ? quad t1/e1/j1 transceiver 44 datasheet los status monitor los r - - - - los3 los2 los1 los0 dfm status monitor dfm r - - - - dfm3 dfm2 dfm1 dfm0 los interrupt enable lie r/w - - - - lie3 lie2 lie1 lie0 dfm interrupt enable die r/w - - - - die3 die2 die1 die0 los interrupt status lis r - - - - lis3 lis2 lis1 lis0 dfm interrupt status dis r - - - - dis3 dis2 dis1 dis0 software reset register res r/w - - - - res3 res2 res1 res0 performance monitoring mon r/w reserve d reserve d reserve d reserve d a3 a2 a1 a0 digital loopback dl r/w - - - - dl3 dl2 dl1 dl0 los/ais criteria select lacs r/w - - - - lacs3 lacs2 lacs1 lacs0 automatic taos select ats r/w - - - - ats3 ats2 ats1 ats0 global control register gcr r/w reserve d raise n cdis coden fifo64 jacf jasel1 jasel0 pulse shaping indirect address register psiad r/w reserve d reserve d reserve d reserve d reserve d lenad2 lenad1 lenad0 pulse shaping data register psdat r/w reserve d reserve d reserve d reserve d reserve d len2 len1 len0 output enable register oer r/w - - - - oe3 oe2 oe1 oe0 ais status register ais r - - - - ais3 ais2 ais1 ais0 ais interrupt enable aisie r/w - - - - aisie3 aisie2 aisie1 aisie0 ais interrupt status aisis r - - - - aisis3 aisis2 aisis1 aisis0 table 8. id register, id (00h) bit name function 7-0 id7-id0 this register contains a unique revision code and is mask programmed. for revision a1, id register = 00h for revision b1, id register = 21h for revision b2, id register = 22h table 9. analog loopback register, aloop (01h) bit name function 3-0 al3-al0 setting a bit to ?1? enables analog local loopback for transceivers 3- 0 respectively. table 7. register bit names (continued) register bit name symrw76543 2 1 0
quad t1/e1/j1 transceiver ? lxt386 datasheet 45 table 10. remote loopback register, rloop (02h) bit name function 3-0 rl3-rl0 setting a bit to ?1? enables remote loopback for transceivers 3-0 respectively. table 11. taos enable register, taos (03h) bit 1 name function 2 3-0 taos3-taos0 setting a bit to ?1? causes a continuous stream of marks to be sent out at the ttip and tring pins of the respective transceiver 3-0. 7-4 - write ?0? to these positions for normal operation. 1. on power up all register bits are set to ?0?. 2. mclk is used as timing reference. if mclk is not available then the channel tclk is used as the reference. this feature is not available in data recovery and line driver mode (mclk= high and tclk = high) table 12. los status monitor register, los (04h) bit 1 name function 3-0 los3-los0 respective bit(s) are set to ?1? every time the los processor detects a valid loss of signal condition in transceivers 3-0. 1. on power up all register bits are set to ?0?. any change in the state causes an interrupt. all los interrupts are cleared by a single read operation. table 13. dfm status monitor register, dfm (05h) bit 1 name function 3-0 dfm3-dfm0 respective bit(s) are set to ?1? every time the short circuit monitor detects a valid secondary output driver short circuit condition in transceivers 3-0. note that dfm is available only in configurations with no transmit series resistors (t1 mode with tvcc=3.3v). 1. on power-up all the register bits are set to ?0?. all dfm interrupts are cleared by a single read operation. table 14. los interrupt enable register, lie (06h) bit 1 name function 3-0 lie3-lie0 transceiver 3-0 los interrupts are enabled by writing a ?1? to the respective bit. 7-4 - write ?0? to these positions for normal operation. 1. on power-up all the register bits are set to ?0?and all interrupts are disabled. table 15. dfm interrupt enable register, die (07h) bit 1 name function 3-0 die3-die0 transceiver 3-0 dfm interrupts are enabled by writing a ?1? to the respective bit. 7-4 - write ?0? to these positions for normal operation. 1. on power-up all the register bits are set to ?0?and all interrupts are disabled.
lxt386 ? quad t1/e1/j1 transceiver 46 datasheet table 16. los interrupt status register, lis (08h) bit name function 3-0 lis3-lis0 these bits are set to ?1? every time a los status change has occurred since the last clear interrupt in transceivers 3-0 respectively. table 17. dfm interrupt status register, dis (09h) bit name function 3-0 dis3-dis0 these bits are set to ?1? every time a dfm status change has occurred since the last cleared interrupt in transceivers 3-0 respectively. table 18. software reset register, res (0ah) bit name function 3-0 res3-res0 writing to this register initiates a 1 microsecond reset cycle, except for intel non- multiplexed mode. when using intel non-multiplexed host mode, extend cycle time to 2 microseconds. please refer to host mode section for more information. this operation sets all lxt386 registers to their default values. table 19. performance monitoring register, mon (0bh) bit name function 3-0 a3:a0 protected monitoring selection. see table 1 on page 11 . 4-7 reserved reserved. table 20. digital loopback register, dl (0ch) bit 1 name function 2 3-0 dl3-dl0 setting a bit to ?1? enables digital loopback for the respective transceiver. 1. on power up all register bits are set to ?0?. 2. during digital loopback los and taos stay active and independent of tclk, while data received on tpos/tneg/tcklk is looped back to rpos/rneg/rclk. table 21. los/ais criteria register, lcs (0dh) bit 1 name function 2 3-0 lcs3-lcs0 1 t1 mode 2 don?t care. t1.231 compliant los/ais detection is used. e1 mode setting a bit to ?1? selects the ets1 300233 los. setting a bit to ?0? selects g.775 los mode. ais works correctly for both etsi and itu when the bit is cleared to ?0?. see errata revision 10.3 or higher for a way to implement etsi los and ais. 1. on power-on reset the register is set to ?0?. 2. t1 or e1 operation mode is determined by the psdr settings.
quad t1/e1/j1 transceiver ? lxt386 datasheet 47 table 22. automatic taos select register, ats (0eh) bit 1 name function 3-0 ats3-ats0 setting a bit to ?1? enables automatic taos generation whenever a los condition is detected in the respective transceiver. 7-4 - write ?0? to these positions for normal operation. 1. on power-on reset the register is set to ?0?. 2. this feature is not available in data recovery and line driver mode (mclk= high and tclk = high) table 23. global control register, gcr (0fh) bit 1 name function 0 jasel0 these bits determine the jitter attenuator position: 1 jasel1 2jacf this bit determines the jitter attenuator low limit 3db corner frequency. refer to the jitter attenuator specifications for details ( table 41 on page 64 ). 3fifo64 this bit determines the jitter attenuator fifo depth: 0 = 32 bit 1 = 64 bit 4coden this bit selects the zero suppression code for unipolar operation mode: 0 = b8zs/hdb3 (t1/e1 respectively) 1 = ami 5 cdis this bit controls enables/disables the short circuit protection feature: 0 = enabled 1 = disabled 6 raisen this bit controls automatic ais insertion in the receive path when los occurs: 0 = receive ais insertion disabled on los 1 = rpos/rneg = ais on los note: this feature is not available in data recovery mode (mclk=high). disable ais interrupts when changing this bit value to prevent inadvertent interrupts. 7-reserved. 1. on power-on reset the register is set to ?0?. jasel0 jasel1 ja position 1 0 transmit path 11 receive path 0 x disabled
lxt386 ? quad t1/e1/j1 transceiver 48 datasheet table 24. pulse shaping indirect address register, psiad (10h) bit 1 name function 0-2 lenad 0-2 the three bit value written to these bits determine the channel to be addressed: 0h = channel 0 1h = channel 1 2h = channel 2 3h = channel 3 data can be read from (written to) the pulse shaping data register (psdat). 3 - 7 - reserved. 1. on power-on reset the register is set to ?0?. table 25. pulse shaping data register, psdat (11h) bit name function 0-2 len 0-2 1, 3 len0-2 determine the lxt386 operation mode: t1 or e1. in addition, for t1 operation, len2-0 set the pulse shaping to meet the t1.102 pulse template at the dsx-1 cross- connect point for various cable lengths: len2 len1 len0 line length cable loss 2 operation mode 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 - 133 ft. abam 133 - 266 ft. abam 266 - 399 ft. abam 399 - 533 ft. abam 533 - 655 ft. abam 0.6 db 1.2 db 1.8 db 2.4 db 3.0 db t1 0 0 0 e1 g.703, 75 coaxial cable and 120 twisted pair cable. e1 3 - 7 - reserved. 1. on power-on reset the register is set to ?0?. 2. maximum cable loss at 772 khz. 3. when reading len, bit values appear inverted. ?b1? revision silicon will fix this so the bits read back correctly. table 26. output enable register, oer (12h) bit 1 name function 3-0 oe3 - oe0 setting a bit to ?1? tristates the output driver of the corresponding transceiver. 1. on power-up all the register bits are set to ?0?. table 27. ais status monitor register, ais (13h) bit 1 name function 3-0 ais3-ais0 respective bit(s) are set to ?1? every time the receiver detects a ais condition in transceivers 3-0. 1. on power-up all the register bits are set to ?0?. all ais interrupts are cleared by a single read operation.
quad t1/e1/j1 transceiver ? lxt386 datasheet 49 table 28. ais interrupt enable register, aisie (14h) bit 1 name function 3-0 aisie3-aisie0 transceiver 3-0 ais interrupts are enabled by writing a ?1? to the respective bit. 7-4 - write ?0? to these positions for normal operation. 1. on power-up all the register bits are set to ?0?. table 29. ais interrupt status register, aisis (15h) bit 1 name function 3-0 aisis3-aisis0 these bits are set to ?1? every time a ais status change has occurred since the last clear interrupt in transceivers 3-0 respectively. 1. on power-up all the register bits are set to ?0?.
lxt386 ? quad t1/e1/j1 transceiver 50 datasheet 5.0 jtag boundary scan 5.1 overview the lxt386 supports ieee 1149.1 compliant jtag boundary scan. boundary scan allows easy access to the interface pins for board testing purposes. in addition to the traditional iee1149.1 digital boundary scan capabilities, the lxt386 also includes analog test port capabilities. this feature provides access to the tip and ring signals in each channel (transmit and receive). this way, the signal path integrity across the primary winding of each coupling transformer can be tested. 5.2 architecture figure 15 represents the lxt386 basic jtag architecture. the lxt386 jtag architecture includes a tap test access port controller, data registers and an instruction register. the following paragraphs describe these blocks in detail. figure 15. lxt386 jtag architecture mux tdo tap controller tck tms trst tdi boundry scan data register bsr analog port scan register asr device identification register idr bypass register byr instruction register ir
quad t1/e1/j1 transceiver ? lxt386 datasheet 51 5.3 tap controller the tap controller is a 16 state synchronous state machine controlled by the tms input and clocked by tck ( figure 16 ).the tap controls whether the lxt386 is in reset mode, receiving an instruction, receiving data, transmitting data or in an idle state. table 30 describes in detail each of the states represented in figure 16 . ta ble 3 0. tap sta te des cription state description test logic reset in this state the test logic is disabled. the device is set to normal operation mode. while in this state, the instruction register is set to the icode instruction. run -test/idle the tap controller stays in this state as long as tms is low. used to perform tests. capture - dr the boundary scan data register (bsr) is loaded with input pin data. shift - dr shifts the selected test data registers by one stage tword its serial output. update - dr data is latched into the parallel output of the bsr when selected. capture - ir used to load the instruction register with a fixed instruction. shift - ir shifts the instruction register by one stage. update - ir loads a new instruction into the instruction register. pause - ir pause - dr momentarily pauses shifting of data through the data/instruction registers. exit1 - ir exit1 - dr exit2 - ir exit2 - dr temporary states that can be used to terminate the scanning process.
lxt386 ? quad t1/e1/j1 transceiver 52 datasheet figure 16. jtag state diagram test-logic reset run test/idle select-dr capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select-ir capture-ir exit1-ir pause-ir exit2-ir update-ir shift-ir 11 1 1 1 1 11 1 1 1 1 1 1 0 0 0 0 0 0 0 0 00 0 0 00 0 1 0 0
quad t1/e1/j1 transceiver ? lxt386 datasheet 53 5.4 jtag register description the following paragraphs describe each of the registers represented in figure 15 . 5.4.1 boundary scan register (bsr) the bsr is a shift register that provides access to all the digital i/o pins. the bsr is used to apply and read test patterns to/from the board. each pin is associated with a scan cell in the bsr register. bidirectional pins or tristatable pins require more than one position in the register. table 1 shows the bsr scan cells and their functions. data into the bsr is shifted in lsb first. example 1. boundary scan register ? bsr (sheet 1 of 3) bit # pin signal i/o type bit symbol comments 0los3o los3 rneg3 o rneg3 n/a - hiz3 hiz3 controls the rpos3, rneg3 and rclk3 pins. setting hiz3 to ?0? enables output on the pins. setting hiz3 to ?1? tristates the pins. rpos3 o rpos3 rclk3 o rclk3 tneg3 i tneg3 tpos3 i tpos3 tclk3 i tclk3 los2 o los2 rneg2 o rneg2 n/a - hiz2 hiz2 controls the rpos2, rneg2 and rclk2 pins. setting hiz2 to ?0? enables output on the pins. setting hiz2 to ?1? tristates the pins. rpos2 o rpos2 rclk2 o rclk2 tneg2 i tneg2 tpos2 i tpos2 tclk2 i tclk2 mclk i mclk mode i mode int o intruptb n/a - sdordyenb sdordyenb controls the ack pin. setting sdordyenb to ?0? enables output on ack pin. setting sdordyenb to ?1? tristates the pin. ack o sdordy ale i ale oe i oe clke i clke a0 i a0 a1 i a1
lxt386 ? quad t1/e1/j1 transceiver 54 datasheet a2 i a2 a3 i a3 a4 i a4 loop0 i/o padd0 loop0 i/o pdo0 loop1 i/o padi1 loop1 i/o pdo1 loop2 i/o padi2 loop2 i/o pdo2 loop3 i/o padi3 loop3 i/o pdo3 loop4 i/o padi4 loop4 i/o pdo4 loop5 i/o padi5 loop5 i/o pdo5 loop6 i/o padi6 loop6 i/o pdo6 loop7 i/o padi7 n/a - pdoenb pdoenb controls the loop0 through loop7 pins. setting pdoenb to ?0? configures the pins as outputs. the output value to the pin is set in pdo[0..7]. setting pdoenb to ?1? tristates all the pins. the input value to the pins can be read in padd[0..7]. loop7 i/o pdo7 cs icsb mux i mux reset irstb mot /intl i imb r/w i rdb ds iwrb tclk1 i tclk1 tpos1 i tpos1 tneg1 i tneg1 rclk1 o rclk1 rpos1 o rpos1 n/a - hiz1 hiz1 controls the rpos1, rneg1 and rclk1 pins. setting hiz1 to ?0? enables output on the pins. setting hiz1 to ?1? tristates the pins. rneg1 o rneg1 los1 o los1 example 1. boundary scan register ? bsr (sheet 2 of 3) bit # pin signal i/o type bit symbol comments
quad t1/e1/j1 transceiver ? lxt386 datasheet 55 tclk0 i tclk0 tpos0 i tpos0 tneg0 i tneg0 rclk0 o rclk0 rpos0 o rpos0 n/a - hiz0 hiz0 controls the rpos0, rneg0 and rclk0 pins. setting hiz0 to ?0? enables output on the pins. setting hiz0 to ?1? tristates the pins. rneg0 o rneg0 los0 o los0 example 1. boundary scan register ? bsr (sheet 3 of 3) bit # pin signal i/o type bit symbol comments
lxt386 ? quad t1/e1/j1 transceiver 56 datasheet 5.5 device identification register (idr) the idr register provides access to the manufacturer number, part number and the lxt386 revision. the register is arranged per ieee 1149.1 and is represented in table 31 . data into the idr is shifted in lsb first. 5.5.1 bypass register (byr) the bypass register is a 1 bit register that allows direct connection between the tdi input and the tdo output. table 31. device identification register (idr) bit # comments 31 - 28 revision number 27 - 12 part number 11 - 1 manufacturer number 0set to ?1?
quad t1/e1/j1 transceiver ? lxt386 datasheet 57 5.5.2 analog port scan register (asr) the asr is a 5 bit shift register used to control the analog test port at pins at1, at2. when the intest_analog instruction is selected, tdi connects to the asr input and tdo connects to the asr output. after 5 tck rising edges, a 5 bit control code is loaded into the asr. data into the asr is shifted in lsb first. table 32 shows the 8 possible control codes and the corresponding operation on the analog port. the analog test port can be used to verify continuity across the coupling transformers primary winding. the analog test port can be used to verify continuity across the coupling transformer?s primary winding as shown in figure 17 . by applying a stimulus to the at1 input, a known voltage will appear at at2 for a given load. this, in effect, tests the continuity of a receive or transmit interface. table 32. analog port scan register ? asr asr control code at1 forces voltage to: at2 senses voltage from: 11111 ttip0 tring0 11110 ttip1 tring1 11101 ttip2 tring2 11100 ttip3 tring3 11011 reserved 11010 reserved 11001 reserved 11000 reserved 10111 rtip0 rring0 10110 rtip1 rring1 10101 rtip2 rring2 10100 rtip3 rring3 10011 reserved 10010 reserved 10001 reserved 10000 reserved
lxt386 ? quad t1/e1/j1 transceiver 58 datasheet 5.5.3 instruction register (ir) the ir is a 3 bit shift register that loads the instruction to be performed. the instructions are shifted lsb first. table 33 shows the valid instruction codes and the corresponding instruction description. table 33. instruction register ? ir instruction code # comments extest 000 connects the bsr to tdi and tdo. input pins values are loaded into the bsr. output pins values are loaded from the bsr. intest_analog 010 connects the asr to tdi and tdo. allows voltage forcing/sensing through at1 and at2. refer to table 32 . sample / preload 100 connects the bsr to tdi and tdo. the normal path between the lxt386 logic and the i/o pins is maintained. the bsr is loaded with the signals in the i/o pins. idcode 110 connects the idr to the tdo pin. bypass 111 serial data from the tdi input is passed to the tdo output through the 1 bit bypass register. figure 17. analog test port application transceiver 2 transceiver 3 rring3 tring3 rtip3 ttip3 rring2 tring2 rtip2 ttip2 transceiver 0 analog mux rring0 rtip0 jtag port asr register at2 at1 1k 1k
quad t1/e1/j1 transceiver ? lxt386 datasheet 59 6.0 test specifications note: table 34 through table 53 and figure 18 through figure 33 represent the performance specifications of the lxt386 and are guaranteed by test except, where noted, by design. the minimum and maximum values listed in table 36 through table 53 are guaranteed over the recommended operating conditions specified in table 35 . table 34. absolute maximum ratings parameter symbol min max unit dc supply voltage vcc -0.5 4.0 v dc supply voltage tvcc 0-3 -0.5 7.0 v input voltage on any digital pin vin gnd-0.5 5.5 v input voltage on rtip, rring 1 vin gnd-0.5 v cc + 0.5 v cc + 0.5 v esd voltage on any pin 2 vin2000?v transient latch-up current on any pin iin 100 ma input current on any digital pin 3 iin -10 10 ma dc input current on ttip, tring 3 iin ? 100 ma dc input current on rtip, rring 3 iin ? 100 ma storage temperature tstor -65 +150 c maximum power dissipation in package p p 830 mw case temperature, 100 pin lqfp package t case ?120 c case temperature, 160 pin pbga package t case ?120 c caution: exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1. referenced to ground. 2. human body model. 3. constant input current. table 35. recommended operating conditions (sheet 1 of 2) parameter len sym min typ max unit test condition digital supply voltage (vcc) vcc 3.135 3.3 3.465 v 3.3v 5% transmitter supply voltage, tvcc=5v nominal tvcc 4.75 5.0 5.25 v 5v 5% transmitter supply voltage, tvcc=3.3v nominal tvcc 3.135 3.3 3.465 v 3.3v 5% ambient operating temperature ta -40 25 +85 c 1. maximum power and current consumption over the full operating temperature and power supply voltage range. includes all channels. 2. power consumption includes power absorbed by line load and external transmitter components. 3. t1 maximum values measured with maximum cable length (len = 111). typical values measured with typical cable length (len = 101). 4. digital inputs are within 10% of the supply rails and digital outputs are driving a 50pf load.
lxt386 ? quad t1/e1/j1 transceiver 60 datasheet average transmitter power supply current, t1 mode 1, 2, 3 i tvcc - 215 110 245 - ma ma 100% 1?s 50% 1?s average digital power supply current 1, 4 i vcc -5060 ma output load at ttip and tring rl 25 ? ? device power consumption mode tvcc load len typ max 1,2 unit test condition e1 3.3v 75 000 - - 440 - mw 50% 1?s - - - 680 mw 100% 1?s 120 000 - - 400 - mw 50% 1?s - - - 600 mw 100% 1?s t1 3 3.3v 100 101-111 - - 550 - mw 50% 1?s - - - 1025 mw 100% 1?s e1 5.0v 75 000 - - 610 - mw 50% 1?s - - - 930 mw 100% 1?s 120 000 - - 540 - mw 50% 1?s - - - 810 mw 100% 1?s t1 3 5.0v 100 101-111 - - 830 - mw 50% 1?s - - - 1400 mw 100% 1?s table 36. dc characteristics (sheet 1 of 2) parameter sym min typ max unit test condition high level input voltage v ih 2? ?v low level input voltage v il ??0.8v high level output voltage 1 v oh 2.4 ? vcc v i out = 400a low level output voltage 1 v ol ??0.4vi out = 1.6ma mode, loop0-3 and jasel low level input voltage vinl ? ? 1/3vcc-0.2 v midrange level input voltage vinm 1/3vcc+0.2 1/2vcc 2/3vcc-0.2 v high level input voltage vinh 2/3vcc+0.2 ? ? v low level input current iinl ? ? 50 a high level input current iinh ? ? 50 a 1. output drivers will output cmos logic levels into cmos loads. table 35. recommended operating conditions (sheet 2 of 2) parameter len sym min typ max unit test condition 1. maximum power and current consumption over the full operating temperature and power supply voltage range. includes all channels. 2. power consumption includes power absorbed by line load and external transmitter components. 3. t1 maximum values measured with maximum cable length (len = 111). typical values measured with typical cable length (len = 101). 4. digital inputs are within 10% of the supply rails and digital outputs are driving a 50pf load.
quad t1/e1/j1 transceiver ? lxt386 datasheet 61 input leakage current iil -10 +10 a tri state leakage current ihz -10 +10 a tri state output current ihz ? ? 1 a ttip, tring line short circuit current ? ? ? 50 ma rms 2 x 11 series resistors and 1:2 transformer input leakage (tms, tdi, trst )? ? ? 50 a table 37. e1 transmit transmission characteristics parameter sym min typ max unit test condition output pulse amplitude 75 120 ? 2.14 2.7 2.37 3.0 2.60 3.3 v v tested at the line side peak voltage of a space 75 120 ? -0.237 -0.3 0.237 0.3 v v transmit amplitude variation with supply ? -1 +1 % difference between pulse sequences ? 200 mv for 17 consecutive pulses pulse width ratio of the positive and negative pulses ? 0.95 1.05 at the nominal half amplitude transmit transformer turns ratio for 75/120 characteristic impedance ? 1:2 rt = 11 1% transmit return loss 75 coaxial cable 1 51khz to 102 khz 102 khz to 2.048 mhz 2.048 mhz to 3.072 mhz ? 15 15 15 17 17 17 ? db db db using components in the lxd384 evaluation board. transmit return loss 120 twisted pair cable 1 51khz to 102 khz 102 khz to 2.048 mhz 2.048 mhz to 3.072 mhz ? 15 15 15 20 20 20 ? db db db using components in the lxd384 evaluation board. transmit intrinsic jitter; 20hz to 100khz ? ? 0.030 0.050 u.i. tx path tclk is jitter free transmit path delay bipolar mode 2 u.i. ja disabled unipolar mode 7 u.i. 1. guaranteed by design and other correlation methods. table 38. e1 receive transmission characteristics (sheet 1 of 2) parameter sym min typ max unit test condition permissible cable attenuation ? ? ? 12 db @1024 khz receiver dynamic range dr 0.5 ? ? vp signal to noise interference margin s/i -15 ? ? db per g.703, o.151 @ 6 db cable attenuation 1. guaranteed by design and other correlation methods. table 36. dc characteristics (sheet 2 of 2) parameter sym min typ max unit test condition 1. output drivers will output cmos logic levels into cmos loads.
lxt386 ? quad t1/e1/j1 transceiver 62 datasheet data decision threshold sre 43 50 57 % rel. to peak input voltage data slicer threshold ? ? 150 ? mv loss of signal threshold ? ? 200 ? mv los hysteresis ? ? 50 ? mv consecutive zeros before loss of signal ? ? 32 2048 ?? g.775 recommendation etsi 300 233 specification los reset ? 12.5% ? ? ? 1?s density low limit input jitter tolerance 1 1hz to 20hz 20hz to 2.4khz 18khz to 100khz ? 36 1.5 0.2 ?? u.i. u.i. u.i. g735 recommendation note 1 cable attenuation is 6 db differential receiver input impedance ? ? 70 ? k @1.024 mhz input termination resistor tolerance ? ? ? 1 % common mode input impedance to ground ? ? 20 ? k input return loss 1 51 khz - 102 khz 102 - 2048 khz 2048khz - 3072 khz ? 20 20 20 ? db db db measured against nominal impedance using components in the lxd384 evaluation board. los delay time ? ? 30 ? s data recovery mode los reset ? 10 ? 255 marks data recovery mode receive intrinsic jitter, rclk output ? ? 0.040 0.0625 u.i. wide band jitter receive path delay bipolar mode 1 u.i. ja disabled unipolar mode 6 u.i. table 39. t1 transmit transmission characteristics (sheet 1 of 2) parameter sym min typ max unit test condition output pulse amplitude ? 2.4 3.0 3.6 v measured at the dsx peak voltage of a space ? -0.15 ? +0.15 v driver output impedance 1 ??1? @ 772 khz transmit amplitude variation with power supply ?-1?+1 % ratio of positive to negative pulse amplitude ? 0.95 ? 1.05 ? t1.102, isolated pulse difference between pulse sequences ? ? ? 200 mv for 17 consecutive pulses, gr-499-core pulse width variation at half amplitude ? ? ? 20 ns jitter added by transmitter 1 10hz - 8khz 8khz - 40khz 10hz - 40khz wide band ??? 0.020 0.025 0.025 0.050 ui pk-pk at&t pub 62411 tclk is jitter free. 1. guaranteed by design and other correlation methods. 2. power measured in a 3 khz bandwidth at the point the signal arrives at the distribution frame for an all 1?s pattern. table 38. e1 receive transmission characteristics (sheet 2 of 2) parameter sym min typ max unit test condition 1. guaranteed by design and other correlation methods.
quad t1/e1/j1 transceiver ? lxt386 datasheet 63 output power levels 2 @ 772 khz @ 1544 khz ? 12.6 -29 ?17.9 dbm dbm t1.102 - 1993 referenced to power at 772 khz transmit return loss 1 51khz to 102 khz 102 khz to 2.048 mhz 2.048 mhz to 3.072 mhz ? 15 15 15 21 21 21 ? db db db with transmit series resistors (tvcc=5v). using components in the lxd384 evaluation board. transmit path delay bipolar mode 2 u.i. ja disabled unipolar mode 7 u.i. table 40. t1 receive transmission characteristics parameter sym min typ max unit test condition permissible cable attenuation ? ? ? 12 db @ 772 khz receiver dynamic range dr 0.5 ? ? vp signal to noise interference margin s/i -16.5 ? ? db @ 655 ft. of 22 abam cable data decision threshold sre 63 70 77 % rel. to peak input voltage data slicer threshold ? ? 150 ? mv loss of signal threshold ? ? 200 ? mv los hysteresis ? ? 50 ? mv consecutive zeros before loss of signal ? 100 175 250 ? t1.231 - 1993 los reset ? 12.5% ? ? ? 1?s density low limit input jitter tolerance 1 0.1hz to 1hz 4.9hz to 300hz 10khz to 100khz - 138 28 0.4 -- u.i. u.i. u.i. at&t pub. 62411 differential receiver input impedance - - 70 - k @772 khz input termination resistor tolerance - - 1 % common mode input impedance to ground - - 20 - k input return loss 1 51 khz - 102 khz 102 - 2048 khz 2048 khz - 3072 khz - 20 20 20 -- db db db measured against nominal impedance. using components in the lxd384 evaluation board. los delay time - - 30 - s data recovery mode los reset - 10 - 255 - data recovery mode receive intrinsic jitter, rclk output 1 - - 0.035 0.0625 u.i. wide band jitter receive path delay bipolar mode 1 u.i. ja disabled unipolar mode 6 u.i. 1. guaranteed by design and other correlation methods. table 39. t1 transmit transmission characteristics (sheet 2 of 2) parameter sym min typ max unit test condition 1. guaranteed by design and other correlation methods. 2. power measured in a 3 khz bandwidth at the point the signal arrives at the distribution frame for an all 1?s pattern.
lxt386 ? quad t1/e1/j1 transceiver 64 datasheet table 41. jitter attenuator characteristics parameter min typ max unit test condition e1 jitter attenuator 3db corner frequency, host mode 1 jacf = 0 32bit fifo -2.5- hz sinusoidal jitter modulation 64bit fifo -3.5- hz jacf = 1 32bit fifo -2.5- hz 64bit fifo -3.5- hz t1 jitter attenuator 3db corner frequency, host mode 1 jacf = 0 32bit fifo -3-hz 64bit fifo -3-hz jacf = 1 32bit fifo -6-hz 64bit fifo -6-hz jitter attenuator 3db corner frequency, hardware mode 1 e1 - 3.5 - hz t1 - 6 - hz data latency delay 32bit fifo -17- ui delay through the jitter attenuator only. add receive and transmit path delay for total throughput delay. 64bit fifo -33- ui input jitter tolerance before fifo overflow or underflow 32bit fifo -24- ui 64bit fifo -56- ui e1 jitter attenuation @ 3 hz @ 40 hz @ 400 hz @ 100 khz -0.5 -0.5 +19.5 +19.5 ? ? db itu-t g.736 ( figure 34 on page 80 ) t1 jitter attenuation @ 1 hz @ 20 hz @ 1 khz @ 1.4 khz @ 70 khz 0 0 33.3 40 40 ??db at&t pub. 62411 ( figure 34 on page 80 ) output jitter in remote loopback 1 0.060 0.11 ui etsi ctr12/13 output jitter 1. guaranteed by design and other correlation methods.
quad t1/e1/j1 transceiver ? lxt386 datasheet 65 table 42. analog test port characteristics parameter sym min typ max unit test condition 3 db bandwidth at13db - 5 - mhz input voltage range at1iv 0 - vcc v output voltage range at2ov 0 - vcc v table 43. transmit timing characteristics parameter sym min typ max unit test condition master clock frequency e1 mclk ? 2.048 ? mhz t1 mclk ? 1.544 ? mhz master clock tolerance ? -100 ? 100 ppm master clock duty cycle ? 40 ? 60 % output pulse width e1 tw 219 244 269 ns t1 tw 291 324 356 ns transmit clock frequency e1 tclke1 - 2.048 - mhz t1 tclkt1 - 1.544 - mhz transmit clock tolerance tclkt -50 ? +50 ppm transmit clock burst rate tclkb - ? 20 mhz gapped transmit clock transmit clock duty cycle tdc 10 ? 90 % nrz mode e1 tpos/tneg pulse width (rz mode) tmpwe1 236 ? 252 ns rz mode (tclk = h for >16 clock cycles) tpos/tneg to tclk setup time tsut 20 - - ns tclk to tpos/tneg hold time tht 20 - - ns delay time oe low to driver high z toez - - 1 s delay time tclk low to driver high z ttz 50 60 75 s figure 18. transmit clock timing diagram tpos tneg tclk tht tsut
lxt386 ? quad t1/e1/j1 transceiver 66 datasheet table 44. receive timing characteristics parameter sym min typ max unit test condition clock recovery capture range e1 ? ? 80 ? ppm relative to nominal frequency mclk = 100 ppm t1 ??180?ppm receive clock duty cycle 1 rckd 40 50 60 % receive clock pulse width 1 e1 tpw 447 488 529 ns t1 tpw 583 648 713 ns receive clock pulse width low time e1 tpwl 203 244 285 ns t1 tpwl 259 324 389 ns receive clock pulse width high time e1 tpwh 203 244 285 ns t1 tpwh 259 324 389 ns rise/fall time 4 tr 20 ? ? ns @ cl=15 pf rpos/rneg pulse width (mclk=h) 2 e1 tpwdl 200 244 300 ns t1 tpwdl 250 324 400 ns rpos/rneg to rclk rising setup time e1 tsu r 200 244 ? ns t1 200 324 ? ns rclk rising to rpos/rneg hold time e1 thr 200 244 ? ns t1 200 324 ? ns delay time between rpos/rneg and rclk ? ? ? 5 ns mclk = h 3 1. rclk duty cycle widths will vary depending on extent of received pulse jitter displacement. maximum and minimum rclk duty cycles are for worst case jitter conditions (0.2ui displacement for e1 per itu g.823). 2. clock recovery is disabled in this mode. 3. if mclk = h the receive plls are replaced by a simple exor circuit. 4. for all digital outputs. figure 19. receive clock timing diagram clke = 0 rpos rneg clke = 1 rpos rneg rclk tpw tpwh tsur tpwl thr thr tsur
quad t1/e1/j1 transceiver ? lxt386 datasheet 67 table 45. jtag timing characteristics parameter sym min typ max unit test conditions cycle time tcyc 200 - - ns j-tms/j-tdi to j-tck rising edge time tsut 50 - - ns j-clk rising to j-tms/l-tdi hold time tht 50 - - ns j-tclk falling to j-tdo valid tdod - - 50 ns figure 20. jtag timing table 46. intel mode read timing characteristics parameter 2 sym min typ 1 max unit test conditions address setup time to latch tsalr 10 ? ? ns valid address latch pulse width tvl 30 ? ? ns latch active to active read setup time tslr 10 ? ? ns chip select setup time to active read tscsr 0 ? ? ns chip select hold time from inactive read thcsr 0 ? ? ns address hold time from inactive ale thalr 5 ns active read to data valid delay time tprd 10 ? 50 ns address setup time to rd inactive thar 1 ? ? ns address hold time from rd inactive tsar 5 ? ? ns inactive read to data tri-state delay time tzrd 3 ? 35 ns valid read signal pulse width tvrd 60 ? ? ns inactive read to inactive int delay time tint ? ? 10 ns active chip select to rdy delay time tdrdy 0 ? 12 ns active ready low time tvrdy ? ? 40 ns inactive ready to tri-state delay time trdyz ? ? 3 ns 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. c l = 100pf on d0-d7, all other outputs are loaded with 50pf. tcyc tsur tht tdod tck tms tdi tdo
lxt386 ? quad t1/e1/j1 transceiver 68 datasheet figure 21. non-multiplexed intel mode read timing rdy tristate tristate address data out tscsr tprd tvrd thcsr tzrd tint tdrdy trdyz tvrdy tdrdy int d7 - d0 rd cs ale a4 - a0 (pulled high) tsar thar
quad t1/e1/j1 transceiver ? lxt386 datasheet 69 figure 22. multiplexed intel read timing table 47. intel mode write timing characteristics (sheet 1 of 2) parameter 2 sym min typ 1 max unit test conditions address setup time to latch tsalw 10 ? ? ns valid address latch pulse width tvl 30 ? ? ns latch active to active write setup time tslw 10 ? ? ns chip select setup time to active write tscsw 0 ? ? ns chip select hold time from inactive write thcsw 0 ? ? ns address hold time from inactive ale thalw 5 ns data valid to write active setup time tsdw 40 ? ? ns data hold time to active write thdw 30 ? ? ns address setup time to wr inactive thaw 2 ? ? ns address hold time from wr inactive tsaw 6 ? ? ns 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. c l = 100pf on d0-d7, all other outputs are loaded with 50pf. 3. these times don?t apply for reset register 0ah, since rdy line goes low once during the cycle. please refer to reset operation and host mode sections for more information. ale rdy tristate tristate address ad7-ad0 data out tvl tslr tscsr tvrd thscr tprd tzrd tint trdyz tvrdy tdrdy tdrdy tsalr thalr cs rd int
lxt386 ? quad t1/e1/j1 transceiver 70 datasheet valid write signal pulse width tvwr 60 ? ? ns inactive write to inactive int delay time tint ? ? 10 ns chip select to rdy delay time 3 tdrdy 0 ? 12 ns active ready low time tvrdy ? ? 40 ns inactive ready to tri-state delay time 3 trdyz ? ? 3 ns figure 23. non-multiplexed intel mode write timing table 47. intel mode write timing characteristics (sheet 2 of 2) parameter 2 sym min typ 1 max unit test conditions 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. c l = 100pf on d0-d7, all other outputs are loaded with 50pf. 3. these times don?t apply for reset register 0ah, since rdy line goes low once during the cycle. please refer to reset operation and host mode sections for more information. a4-a0 ale d7-d0 rdy tristat e tristate address cs wr int tscsw tvwr tdrdy tvrdy thcsw write data tsdw thdw tint tdrdy trdyz (pulled high) tsaw thaw
quad t1/e1/j1 transceiver ? lxt386 datasheet 71 figure 24. multiplexed intel mode write timing table 48. motorola bus read timing characteristics parameter 2 sym min typ 1 max unit test conditions address setup time to address or data strobe tsar 10 ? ? ns address hold time from address or data strobe thar 5 ? ? ns valid address strobe pulse width tvas 95 ? ? ns r/w setup time to active data strobe tsrw 10 ? ? ns r/w hold time from inactive data strobe thrw 0 ? ? ns chip select setup time to active data strobe tscs 0 ? ? ns chip select hold time from inactive data strobe thcs 0 ? ? ns address strobe active to data strobe active delay tasds 20 ? ? ns delay time from active data strobe to valid data tpds 3 ? 30 ns delay time from inactive data strobe to data high z tdz 3 ? 30 ns valid data strobe pulse width tvds 60 ? ? ns inactive data strobe to inactive int delay time tint ? ? 10 ns data strobe inactive to address strobe inactive delay tdsas 15 ? ? ns ds asserted to ack asserted delay tdackp ? ? 40 ns ds deasserted to ack deasserted delay tdack ? ? 10 ns active ack to valid data delay tpack ? ? 0 ns 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. c l = 100pf on d0-d7, all other outputs are loaded with 50pf. ale ad7-ad0 rdy tristate tristate address wr cs int tvl tslw tscsw thalw tsalw tdrdy tvrdy tvwr thcsw tsdw write data thdw tint tdrdy tdrdy z
lxt386 ? quad t1/e1/j1 transceiver 72 datasheet figure 25. non-multiplexed motorola mode read timing a4-a0 d7-d0 address data out as r/w cs ds int ack tsar thar tscs thrw thcs tdz tint tdack tpack tdackp tpds tvds tsrw (pulled high)
quad t1/e1/j1 transceiver ? lxt386 datasheet 73 figure 26. multiplexed motorola mode read timing table 49. motorola mode write timing characteristics (sheet 1 of 2) parameter 2 sym min typ 1 max unit test conditions address setup time to address strobe tsas 10 ? ? ns address hold time to address strobe thas 5 ? ? ns valid address strobe pulse width tvas 95 ? ? ns r/w setup time to active data strobe tsrw 10 ? ? ns r/w hold time from inactive data strobe thrw 0 ? ? ns chip select setup time to active data strobe tscs 0 ? ? ns chip select hold time from inactive data strobe thcs 0 ? ? ns address strobe active to data strobe active delay tasds 20 ? ? ns data setup time to ds deassertion tsdw 40 ? ? ns data hold time from ds deassertion thdw 30 ? ? ns valid data strobe pulse width tvds 60 ? ? ns inactive data strobe to inactive int delay time tint ? ? 10 ns 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. c l = 100pf on d0-d7, all other outputs are loaded with 50pf. d7-d0 data out tsrw tscs tasds tvds tsar thar tpds address tdackp tpack tdsas tvas thrw thcs tdz tint tdack as r/w cs ds int ack
lxt386 ? quad t1/e1/j1 transceiver 74 datasheet data strobe inactive to address strobe inactive delay tdsas 15 ? ? ns active data strobe to ack output enable time tdack 0 ? 12 ns ds asserted to ack asserted delay tdackp ? 40 ns figure 27. non-multiplexed motorola mode write timing table 49. motorola mode write timing characteristics (sheet 2 of 2) parameter 2 sym min typ 1 max unit test conditions 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. c l = 100pf on d0-d7, all other outputs are loaded with 50pf. a4-a0 address d7-d0 tsas thas tsrw tscs tvds tdackp thrw thcs tsdw thdw write data tint tdack as r/w cs int ack ds (pulled high)
quad t1/e1/j1 transceiver ? lxt386 datasheet 75 g figure 28. multiplexed motorola mode write timin table 50. serial i/o timing characteristics parameter sym min typ 1 max unit test condition rise/fall time any pin trf - - 100 ns load 1.6ma, 50 pf sdi to sclk setup time tdc 5 - - ns sclk to sdi hold time tcdh 5 - - ns sclk low time tcl 25 - - ns sclk high time tch 25 - - ns sclk rise and fall time tr, tf - - 50 ns cs falling edge to sclk rising edge tcc 10 - - ns last sclk edge to cs rising edge tcch 10 - - ns cs inactive time tcwh 50 - - ns sclk to sdo valid delay time tcdv - - 5 ns sclk falling edge or cs rising edge to sdo high z tcdz - 10 - ns 1. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. address d7-d0 tdsas thrw thcs thdw tint tdack tsdw write data tdackp tvds tasds tsas thas tsrw tvas tscs as r/w cs ds int ack
lxt386 ? quad t1/e1/j1 transceiver 76 datasheet figure 29. serial input timing figure 30. serial output timing table 51. transformer specifications 3 tx/rx turns ratio 1 primary inductance mh (min.) leakage inductance h (max.) interwinding capacitance pf (max.) dcr (max.) dielectric breakdown vo lta ge v 2 (min.) tx 1:2 1.2 0.60 60 0.70 pri 1.20 sec 1500 vrms rx 1:2 1.2 0.60 60 1.10 pri 1.10 sec 1500 vrms 1. transformer turns ratio accuracy is 2%. 1. this parameter is application dependent.liu side: line side. 2. refer to the faq or application note 118 for recommended magnetics. t ch t cc t cl t cdh t dc t cdh t cch t cwh cs sclk sdi lsb lsb msb control byte data byte t cch 1 2345678910111213141516 0123 4 567 1 2345678910111213141516 t cdz t cch t cdz clke = 0 clke = 1 sclk cs cs sdo sclk 0123 4 567 sdo
quad t1/e1/j1 transceiver ? lxt386 datasheet 77 table 52. g.703 2.048 mbit/s pulse mask specifications parameter cable unit twp coax test load impedance 120 75 nominal peak mark voltage 3.0 2.37 v nominal peak space voltage 0 0.30 0 0.237 v nominal pulse width 244 244 ns ratio of positive and negative pulse amplitudes at center of pulse 95-105 95-105 % ratio of positive and negative pulse amplitudes at nominal half amplitude 95-105 95-105 % figure 31. e1, g.703 mask templates table 53. t1.102 1.544 mbit/s pulse mask specifications parameter cable unit twp test load impedance 100 nominal peak mark voltage 3.0 v nominal peak space voltage 0 0.15 v nominal pulse width 324 ns ratio of positive and negative pulse amplitudes 95-105 % 20% 0% (244-25) 219 ns 244 ns nominal pulse 488 ns (244+244) 10% 50% 194 ns 269 ns (244+25) 10% (244- 50) 10% 10% 10% 10% 20% 20% v = 100%
figure 32. t1, t1.102 mask templates -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 -0.80 -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 tim e [ui] normalized amplitude
quad t1/e1/j1 transceiver ? lxt386 datasheet 79 figure 33. lxt386 jitter tolerance performance jitter 1 hz 10 hz 100 hz 1 khz 10 khz 100 kh z frequency .1 ui 1 ui 10 ui 100 ui 1000 ui 1.5 ui @ 20 hz 1.5 ui @ 2.4 khz 0.2 ui @ 18 khz itu g.823, mar 1993 (e1) 18 ui @ 1.8 hz at&t 62411, dec 1990 (t1) 28 ui @ 4.9 hz 28 ui @ 300 hz 0.4 ui @ 10 khz gr-499-core, dec 1995 (t1) 5 ui @ 500 hz 0.1 ui @ 8 khz lxt386 typ.
lxt386 ? quad t1/e1/j1 transceiver 80 datasheet figure 34. jitter transfer performance e1 t1 -60 db -40 db -30 db -20 db -10 db 0 db 10 db gain 0.5 db @ 40hz -19.5 db @ 400 hz -19.5 db @ 20 khz itu g.736 template 0.5 db @ 3hz 1 hz 10 hz 100 hz 1 khz 10 khz 100 kh z frequency -80 db lxt386 typ. f 3db =2.5 hz f 3db =3.5 hz -60 db -40 db -30 db -20 db -10 db 0 db 10 db gain 0 db @ 1 hz 0 db @ 20 hz -33.3 db @ 1 khz -40 db @ 70 khz -60 db @ 57 hz -6 db @ 2 hz -40 db @ 1.4 khz tr-tsy-000009 0.5 db @ 350 hz -33.7 db @ 2.5khz -49.2 db @ 15khz 0.1 db @ 40 hz gr-253-core at&t pub 62411 frequency 1 hz 10 hz 100 hz 1 khz 10 khz 100 kh z -80 db f 3db = 3 hz f 3db = 6 hz lxt386 typ.
quad t1/e1/j1 transceiver ? lxt386 datasheet 81 6.1 recommendations and specifications at&t pub 62411 ansi t1.102 - 199x digital hierarchy electrical interface ansi t1.231 -1993 digital hierarchy layer 1 in-service digital transmission performance monitoring bellcore tr-tsy-000009 asynchronous digital multiplexes requirements and objectives bellcore gr-253-core sonet transport systems common generic criteria bellcore gr-499-core transport systems generic requirements g.703 physical/electrical characteristics of hierarchical digital interfaces g. 704 functional characteristics of interfaces associated with network nodes g.735 characteristics of primary pcm multiplex equipment operating at 2048 kbit/s and offering digital access at 384 kbit/s and/or synchronous digital access at 64 kbit/s g.736 characteristics of a synchronous digital multiplex equipment operating at 2048 kbit/s g.772 protected monitoring points provided on digital transmission systems g.775 loss of signal (los) and alarm indication (ais) defect detection and clearance criteria g.783 characteristics of synchronous digital hierarchy (sdh) equipment functional blocks g.823 the control of jitter and wander within digital networks which are based on the 2048 kbit/ s hierarchy o.151 specification of instruments to measure error performance in digital systems oftel otr-001 short circuit current requirements ets 300166 physical and electrical characteristics ets 300386-1 electromagnetic compatibility requirement figure 35. output jitter for ctr12/13 applications 0.2 0.15 0.1 0.05 0 10 hz 100 hz 1 khz 10 khz 100 khz frequency jitter amplitude (ulpp) 20 hz lxt386 typ, f 3db = 2.5hz & 3.5 hz
lxt386 ? quad t1/e1/j1 transceiver 82 datasheet 7.0 mechanical specifications figure 36. 60 plastic ball grid array (pbga) package dimensions 15.00 13.00 0.20 4.72 0.10 4.72 0.10 ?1.00 (3 plcs) pin #a1 corner 15.00 13.00 0.20 pin #a1 id 1.61 0.19 0.40 0.10 0.36 0.04 0.85 seating plane 13.00 1.00 0.50 0.10 1.00 1.00 ref 13 .00 1.00 r 14 13 12 11 10 9 8 7 6 5 4 3 2 1 p n m l k j h g f e d c b a bottom view top view side view note: 1. all dimensions in millimeters. 2. all dimensions and tolerances conform to asme y 14.5m-1994. 3. tolerance = 0.05 unless specified otherwise. 160 pbga package ? part number lxt386be ? extended temperature range (-40 c to 85 c)
quad t1/e1/j1 transceiver ? lxt386 datasheet 83 figure 37. 100 pin low quad flat packages (lqfp) dimensions 12.00 bsc 14.00 bsc 16.00 bsc 12.00 bsc 14.00 bsc 16.00 bsc 1 23 0.22 0.05 1.00 ref 0.20 min 0.60 0.15 detail "a" 0.50 bsc pin #1 index all dimensions in millimeters all dimensions and tolerances conform to ansi y14.5m-1982. see detail "a " 1.60 max 1.40 0.05 0.05 min 0.15 max 100 pin lqfp ? part number lxt386le ? extended temperature range (-40 c to 85 c)
lxt386 ? quad t1/e1/j1 transceiver 84 datasheet 7.1 top label markings figure 38 shows a sample lqfp non-rohs package for the lxt386 transceiver. in contrast to pb-free (rohs-compliant) lqfp packages, the non-rohs-compliant packages do not have the ?e3? symbol in the last line of the package label. figure 39 shows a sample lqfp rohs package for the lxt386 transceiver. figure 38. sample lqfp non-rohs package - intel ? lxt386 transceiver pin 1 lxt386le b2 xxxxxxxx part number fpo number bsmc bottom side mark code b5411-01 figure 39. sample lqfp rohs package - intel ? lxt386 transceiver pin 1 wjlxt386e b2 xxxxxxxx part number fpo number e3 pb- free indication bsmc bottom side mark code b5412-02
quad t1/e1/j1 transceiver ? lxt386 datasheet 85 8.0 product ordering information table 54 lists product ordering information for the lxt386 transceiver. table 54. product ordering information product number revision package type pin count rohs compliant figure djlxt386le.b2 b2 lqfp 100 no figure 38, ?sample lqfp non-rohs package - intel? lxt386 transceiver? wjlxt386le.b2 b2 lqfp 100 yes figure 39, ?sample lqfp rohs package - intel? lxt386 transceiver?
lxt386 ? quad t1/e1/j1 transceiver 86 datasheet 9.0 package information figure 40 shows an order matrix with sample information on how to order a lxt386 product. figure 40. order matrix dj e 386 l lxt b2 product revision xn = 2 alphanumeric characters temperature range a = ambient (0 ? 55 0 c) c = commercial (0 ? 70 0 c) e = extended (-40 ? 85 0 c) internal package designator l = lqfp p = plcc n = dip q = pqfp h = qfp t = tqfp b = bga c = cbga e = tbga k = hsbga (bga with heat slug product code xxxxx = 3-5 digit alphanumeric ixa product prefix lxt = phy layer device ixe = switching engine ixf = formatting device (mac/framer) ixp = network processor intel package designator b5465-01 pb-free wb bj ja wd qu eg wg ub uc ep ee ru pc el pr lu ew wf jp package leaded sc hqfp tqfp tqfp pqfp pqfp pqfp ssop qfn qfn pdip plcc mmap mmap pbga pbga pbga cbga fcbga tbga pbga hb fa fa hd ku s hg lb pd pa n hz rc fl fw gd gw hf hl tl wj lqfp dj

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